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STTS2004 数据表(PDF) 36 Page - STMicroelectronics

部件名 STTS2004
功能描述  16 bytes Page Write within 5 ms
PDF  58 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STTS2004 数据表(HTML) 36 Page - STMicroelectronics

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SPD EEPROM operation
STTS2004
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DocID024229 Rev 3
5.5.1
Byte write
After the device select code and the address byte, the bus master sends one data byte. If
the addressed location is hardware write-protected, the device replies to the data byte with
NoAck, and the location is not modified. If, instead, the addressed location is not write-
protected, the device replies with Ack. The bus master terminates the transfer by generating
a Stop condition, as shown in Figure 13.
Figure 13. Write mode sequences in a non write-protected area
5.5.2
Page write
The Page write mode allows up to 16 bytes to be written in a single Write cycle, provided
that they are all located in the same page in the memory: that is, the most significant
memory address bits are the same. If more bytes are sent than will fit up to the end of the
page, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to
become overwritten in an implementation dependent way.
The bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the
device if Write Control (WC) is low. If the addressed location is hardware write-protected,
the device replies to the data byte with NoAck, and the locations are not modified. After
each byte is transferred, the internal byte address counter (the 4 least significant address
bits only) is incremented. The transfer is terminated by the bus master generating a Stop
condition.
5.5.3
Minimizing system delays by polling on ACK
The sequence, as shown in Figure 14, is:
Initial condition: a Write cycle is in progress.
Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
Byte Write
Device select
Byte address
Data in
Page Write
Device select
Byte address
Data in 1
Data in 2
AI01941b
Data in N
ACK
ACK
ACK
R/W
ACK
ACK
ACK
R/W
ACK
ACK



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