STTS2004 datasheet(32/58 Pages) STMICROELECTRONICS

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Temperature sensor registers

STTS2004

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DocID024229 Rev 3

4.9

Device reset and initialization

In order to prevent inadvertent operations during power-up, a Power-On Reset (POR) circuit

is included. Upon a cold power-on, VDD must rise monotonically between VPON and VDD

(min) without ringback to ensure proper startup. Once VDD has passed the VPON threshold,

the device is reset.

Prior to selecting the memory and issuing instructions, a valid and stable VDD voltage must

be applied, and no command may be issued to the device for tINIT. The supply voltage must

remain stable and valid until the end of the transmission of the instruction and, for a Write

instruction, until the completion of the internal write cycle (tW).

At power-down (phase during which VDD decreases continuously), as soon as VDD drops

from the normal operating voltage below the minimum operating voltage, the device stops

responding to commands. Upon warm power cycling, VDD must remain below VPOFF for the

period tPOFF, and must meet cold power-on reset timing when restoring power.

Note:

If VDD drops below VPON but stays above VPOFF, for less than or greater than tPOFF, and

then returns to VDD(min), a POR MAY occur.

Figure 11. STTS2004 reset and initialization

Power-up conditions

The VDD voltage has to rise continuously from 0 V up to the minimum VDD operating voltage

defined in Table 29 and the rise time must not vary faster than 1 V/μs.

VPOFF

VPON

VDD (min)

Cold Power

Warm Power

On Reset

VDD Ramp Up and Ramp Down

tPOFF

First

Command

tINIT

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