STTS2004 datasheet(47/58 Pages) STMICROELECTRONICS

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STTS2004

DC and AC parameters

Table 33. AC characteristics of STTS2004 for SMBus and I2C compatibility timings

Symbol

Parameter

Min

Max

Units

fSCL

I2C clock frequency

1000

kHz

tHIGH

Clock high period

260

–

tLOW(1)

1. The STTS2004 will not initiate clock stretching which is an I2C bus optional feature.

Clock low period

500

–

tR(2)

2. Guaranteed by design and characterization, not necessarily tested.

Clock/data rise time

–

120

tF(2)

Clock/data fall time

–

120

tSU:DAT

Data-in setup time

–

tHD:DI

Data-in hold time

–

tHD:DAT

Data-out hold time

350

tSU:STA(3)

3. For a restart condition, or following a WRITE cycle.

Repeated start condition setup time

260

–

tHD:STA

Hold time after (repeated) start condition. After this period,

the first clock cycle is generated.

260

–

tSU:STO

Stop condition setup time

260

–

tBUF

Bus free time between stop (P) and start (S) conditions

500

–

tW(4)

4. This parameter reflects maximum WRITE time for EEPROM.

WRITE time for EEPROM

–

ttimeout(5)

5. The I2C bus masters can terminate a transaction in process and reset devices on the bus by asserting SCL

low for tTIMEOUT,MAX or longer. The STTS2004, upon detecting this condition, will reset communication and

be able to receive a new START condition no later than tTIMEOUT,MAX. The STTS2004 will not reset if SCL

stretching is less than tTIMEOUT,MIN.

Bus timeout

tPOFF

Warm power cycle off time

–

tINIT

Time from power-on to first command

–

CB(6)

6. The maximum bus capacitance allowable may vary from this value depending on the actual operating

voltage and frequency of the application.

Capacitive load for each bus line

550

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