SPC560P50L5 datasheet(7/112 Pages) STMICROELECTRONICS

7 / 112 page

SPC560P44Lx, SPC560P50Lx

Introduction

Doc ID 14723 Rev 9

7/112

Introduction

1.1

Document overview

This document provides electrical specifications, pin assignments, and package diagrams

for the SPC560P44/50 series of microcontroller units (MCUs). It also describes the device

features and highlights important electrical and physical characteristics. For functional

characteristics, refer to the device reference manual.

1.2

Description

This 32-bit system-on-chip (SoC) automotive microcontroller family is the latest

achievement in integrated automotive application controllers. It belongs to an expanding

range of automotive-focused products designed to address chassis applications—

specifically, electrical hydraulic power steering (EHPS) and electric power steering (EPS)—

as well as airbag applications.

This family is one of a series of next-generation integrated automotive microcontrollers

based on the Power Architecture technology.

The advanced and cost-efficient host processor core of this automotive controller family

complies with the Power Architecture embedded category. It operates at speeds of up to

64 MHz and offers high performance processing optimized for low power consumption. It

capitalizes on the available development infrastructure of current Power Architecture

devices and is supported with software drivers, operating systems and configuration code to

assist with users implementations.

1.3

Device comparison

Table 2 provides a summary of different members of the SPC560P44Lx, SPC560P50Lx

family and their features—relative to full-featured version—to enable a comparison among

the family members and an understanding of the range of functionality offered within this

family.

Table 2.

SPC560P44Lx, SPC560P50Lx device comparison

Feature

SPC560P44

SPC560P50

Code flash memory (with ECC)

384 KB

512 KB

Data flash memory / EE option (with ECC)

64 KB

SRAM (with ECC)

36 KB

40 KB

Processor core

32-bit e200z0h

Instruction set

VLE (variable length encoding)

CPU performance

0–64 MHz

FMPLL (frequency-modulated phase-locked loop)

module

INTC (interrupt controller) channels

147

PIT (periodic interrupt timer)

1 (includes four 32-bit timers)

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