SPC560P50L5 datasheet(18/112 Pages) STMICROELECTRONICS

18 / 112 page

Introduction

SPC560P44Lx, SPC560P50Lx

18/112

Doc ID 14723 Rev 9

1.5.13

System timer module (STM)

The STM module implements these features:

●

One 32-bit up counter with 8-bit prescaler

●

Four 32-bit compare channels

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Independent interrupt source for each channel

●

Counter can be stopped in debug mode

1.5.14

Software watchdog timer (SWT)

The SWT has the following features:

●

32-bit time-out register to set the time-out period

●

Programmable selection of system or oscillator clock for timer operation

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Programmable selection of window mode or regular servicing

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Programmable selection of reset or interrupt on an initial time-out

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Master access protection

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Hard and soft configuration lock bits

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Reset configuration inputs allow timer to be enabled out of reset

1.5.15

Fault collection unit (FCU)

The FCU provides an independent fault reporting mechanism even if the CPU is

malfunctioning.

The FCU module has the following features:

●

FCU status register reporting the device status

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Continuous monitoring of critical fault signals

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User selection of critical signals from different fault sources inside the device

●

Critical fault events trigger 2 external pins (user selected signal protocol) that can be

used externally to reset the device and/or other circuitry (for example, safety relay or

FlexRay transceiver)

●

Faults are latched into a register

1.5.16

System integration unit – Lite (SIUL)

The SPC560P44Lx, SPC560P50Lx SIUL controls MCU pad configuration, external

interrupt, general purpose I/O (GPIO), and internal peripheral multiplexing.

The pad configuration block controls the static electrical characteristics of I/O pins. The

GPIO block provides uniform and discrete input/output control of the I/O pins of the MCU.

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