SPC560P50L5 datasheet(17/112 Pages) STMICROELECTRONICS

17 / 112 page

SPC560P44Lx, SPC560P50Lx

Introduction

Doc ID 14723 Rev 9

17/112

1.5.9

Frequency-modulated phase-locked loop (FMPLL)

The FMPLL allows the user to generate high speed system clocks from a 4–40 MHz input

clock. Further, the FMPLL supports programmable frequency modulation of the system

clock. The PLL multiplication factor, output clock divider ratio are all software configurable.

The PLL has the following major features:

●

Input clock frequency: 4–40 MHz

●

Maximum output frequency: 64 MHz

●

Voltage controlled oscillator (VCO)—frequency 256–512 MHz

●

Reduced frequency divider (RFD) for reduced frequency operation without forcing the

PLL to relock

●

Frequency-modulated PLL

–

Modulation enabled/disabled through software

–

Triangle wave modulation

●

Programmable modulation depth (±0.25% to ±4% deviation from center frequency):

programmable modulation frequency dependent on reference frequency

●

Self-clocked mode (SCM) operation

1.5.10

Main oscillator

The main oscillator provides these features:

●

Input frequency range: 4–40 MHz

●

Crystal input mode or oscillator input mode

●

PLL reference

1.5.11

Internal RC oscillator

This device has an RC ladder phase-shift oscillator. The architecture uses constant current

charging of a capacitor. The voltage at the capacitor is compared by the stable bandgap

reference voltage.

The RC oscillator provides these features:

●

Nominal frequency 16 MHz

●

±5% variation over voltage and temperature after process trim

●

Clock output of the RC oscillator serves as system clock source in case loss of lock or

loss of clock is detected by the PLL

●

RC oscillator is used as the default system clock during startup

1.5.12

Periodic interrupt timer (PIT)

The PIT module implements these features:

●

4 general purpose interrupt timers

●

32-bit counter resolution

●

Clocked by system clock frequency

●

Each channel can be used as trigger for a DMA request

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