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ST7MC1K2 数据表(PDF) 263 Page - STMicroelectronics |
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ST7MC1K2 数据表(HTML) 263 Page - STMicroelectronics |
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263 / 371 page  Obsolete Product(s) - Obsolete Product(s) ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto On-chip peripherals 263/371 Interrupt mask register (MIMR) MIMR Reset value: 0000 0000 (00h) 7 654 32 10 PUM SEM RIM CLIM EIM ZIM DIM CIM R/W R/W R/W R/W R/W R/W R/W R/W Table 124. MIMR register description Bit Name Function 7 PUM PWM update mask bit 0: PWM update interrupt disabled 1: PWM update interrupt enabled 6 SEM Speed error mask bit 0: Speed error interrupt disabled 1: Speed error interrupt enabled 5RIM Ratio update interrupt mask bit 0: Ratio update interrupts (R+ and R-) disabled 1: Ratio update interrupts (R+ and R-) enabled 4CLIM Current limitation interrupt mask bit 0: Current limitation interrupt disabled 1: Current limitation interrupt enabled This interrupt is available only in voltage mode (VOC1 bit = 0 in MCRA register) and occurs when the motor current feedback reaches the external current limitation value. 3EIM Emergency stop interrupt mask bit 0: Emergency stop interrupt disabled 1: Emergency stop interrupt enabled 2ZIM Back EMF zero-crossing interrupt mask bit 0: BEMF Zero-crossing Interrupt disabled 1: BEMF Zero-crossing Interrupt enabled 1DIM End of demagnetization interrupt mask bit 0: End of demagnetization interrupt disabled 1: End of demagnetization interrupt enabled if the HDM or SDM bit in the MCRB register is set 0CIM Commutation/capture interrupt mask bit 0: Commutation/capture interrupt disabled 1: Commutation/capture interrupt enabled Obsolete Product(s) - Obsolete Product(s) |
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