ST7MC1K2 datasheet(266/371 Pages) STMICROELECTRONICS

266 / 371 page

Obsolete

Product(s)

- Obsolete

Product(s)

On-chip peripherals

ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto

266/371

6CKE

Clock enable bit

0: Motor control peripheral clocks disabled

1: Motor control peripheral clocks enabled

Note: ‘Clocks disabled’ means that all peripheral internal clocks (delay manager,

internal sampling clock, PWM generator) are disabled. Therefore, the peripheral can

no longer detect events and the preload registers do not operate. When clocks are

disabled, write accesses are allowed, so for example, MTIM counter register can be

reset by software. See Table 127.

5SR

Sensor ON/OFF

0: Sensorless mode

1: Position sensor mode

See Table 128, Table 133 and Table 134.

4DAC

Direct access to phase state register

0: No direct access (reset value). In this mode the preload value of the MPHST and

MCRB registers is taken into account at the C event

1: Direct access enabled. In this mode, write a value in the MPHST register to access

the outputs directly

See Table 129.

Note: In direct access mode (DAC bit is set in MCRA register), a C event is generated

as soon as there is a write access to the OO[5:0] bits in MPHST register. In this case,

the PWM low/high selection is done by the OS0 bit in the MCRB register.

3V0C1

Voltage/current mode

0: Voltage mode

1: Current mode

2SWA

Switched/autoswitched mode

0: Switched mode

1: Autoswitched mode

Notes:

1. After reset, in autoswitched mode (SWA = 1), the motor control peripheral is waiting

for a C commutation event.

2. After reset, a C event is immediately generated when CKE and SWA are

simultaneously set due to a nil value of MCOMP.

1PZ

Protection from parasitic zero-crossing event detection

0: Protection disabled

1: Protection enabled

Note: If the PZ bit is set, the Z event filter (ZEF[3:0] in the MZFR register is ignored.

DCB

Data capture bit

0: Use MZPRV (ZN-1) for multiplication

1: Use MZREG (ZN) for multiplication

See Table 130.

The reset state is either high impedance, high or low state depending on the corresponding option bit.

When the MOE bit in the MCRA register is reset (MCOx outputs in reset state), and the SR bit in the MCRA

frequency) then, depending on the state of the ZSV bit in the MSCR register, Z event sampling can run or

be stopped (and D event is sampled).

Table 126.

MCRA register description (continued)

Bit Name

Function

Obsolete

Product(s)

- Obsolete

Product(s)

ST7MC1K2 数据表(PDF) 266 Page - STMicroelectronics

ST7MC1K2 数据表(HTML) 266 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

ST7MC1K2 数据表(PDF) 266 Page - STMicroelectronics

ST7MC1K2 数据表(HTML) 266 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载