ST7MC1K2 datasheet(267/371 Pages) STMICROELECTRONICS

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On-chip peripherals

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Table 127.

Output configuration summary(1)

When clocks are disabled (CKE bit reset) while outputs are enabled (MOE bit set), the effects on the MCOx

outputs where PWM signal is applied depend on the running mode selected:

- In voltage mode (VOC1 bit = 0), the MCOx outputs where PWM signal is applied stay at level 1.

- In current mode (VOC1 bit = 1), the MCOx outputs where PWM signal is applied are put to level 0.

In all cases, MCOx outputs where a level 1 was applied before disabling the clocks stay at level 1. That is

why it is recommended to disable the MCOx outputs (reset MOE bit) before disabling the clocks. This puts

all the MCOx outputs under reset state defined by the corresponding option bit.

Effect on PWM generator: The PWM generator 12-bit counter is reset as soon as CKE = 0. This ensures

that the PWM signals start properly in all cases. When these bits are set, all registers with preload on

update event are transferred to active registers.

CKE bit

MOE bit DAC bit Peripheral clock

Effect on MCOx output

Disabled

Reset state

Disabled

Peripheral frozen(2)

“Peripheral frozen” configuration is not recommended, as the peripheral may be stopped in an unknown

state (depending on PWM generator outputs,etc.). It is better practice to exit from run mode by first setting

output state (by toggling either MOE or DAC bits) and then to disabling the clock if needed.

Disabled

Direct access via MPHST (only logical level)(3)

In direct access mode (DAC = 1), when CKE = 0 (peripheral clock disabled) only logical level can be

applied on the MCOx outputs when they are enabled whereas when CKE = 1 (peripheral clock enabled), a

PWM signal can be applied on them. Refer to Table 155: Deadtime generator set-up on page 281.

Enabled

Reset state

Enabled

Standard running mode.

Enabled

Direct access via MPHST (PWM can be applied)(3)

Table 128.

Sensor mode selection

SR bit

Mode

OS[2:0] bits

Behavior of the output PWM

Sensors not used OS[2:0] bits enabled

‘Between Cn and D’ behavior,

‘Between D and Z’ behavior and

‘Between Z and Cn+1’ behavior

Sensors used

OS1 disabled

‘Between Cn and Z’ behavior and

‘Between Z and Cn+1’ behavior

Table 129.

DAC bit meaning

MOE bit

DAC bit

Effect on output

Reset state depending on the option bit

Standard running mode

MPHST register value (depending on MPOL, MPAR register values

and PWM setting) (see Table 155)

Table 130.

Multiplier result

DCB bit

Commutation delay

MCOMP = MWGHT x MZPRV/256

MCOMP = MWGHT x MZREG/256

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