ST7MC1K2 datasheet(270/371 Pages) STMICROELECTRONICS

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Warning:

As the MCRB register contains preload bits with, it has to be

written as a complete byte. A bit set or bit reset instruction on

a non-preload bit resets has the effect of resetting all the

preload bits.

Control register C (MCRC)

MCRB

Reset value: 0000 0000 (00h)

654

SEI/OI

EDIR/HZ

SPLG

VR[2:0]

R/W

Table 136.

MCRC register description

Bit

Name

Function

SEI/OI

Speed error interrupt flag/MTIM overflow flag

Position sensor or sensorless mode (TES[1:0] bits = 00):

OI: MTIM overflow flag

This flag signals an overflow of the MTIM timer. It has to be cleared by software.

0: No MTIM timer overflow

1: MTIM timer overflow

Note: No interrupt is associated with this flag.

Speed sensor mode (TES[1:0] bits = 01, 10, 11):

SEI: Speed error interrupt flag

0: No tacho error interrupt pending

1: Tacho error interrupt pending

EDIR/HZ

Encoder Direction bit/ Hardware zero-crossing event bit

Position sensor or sensorless mode (TES[1:0] bits = 00):

HZ: Hardware zero-crossing event bit

This read/write bit selects if the Z event is hardware or not.

0: No hardware zero-crossing event

1: Hardware zero-crossing event

Speed sensor mode (TES[1:0] bits = 01, 10, 11):

EDIR: Encoder direction bit

This bit is read-only. As the rotation direction depends on encoder outputs and

motor phase connections, this bit cannot indicate absolute direction. It therefore

gives the relative phase-shift (that is, advance/delay) between the two signals in

quadrature output by the encoder (see Figure 91).

0: MCIA input delayed compared to MCIB input

1: MCIA input in advance compared to MCIB input

5SZ

Simulated zero-crossing event bit

0: No simulated zero-crossing event

1: Simulated zero-crossing event

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