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ST72321R7-Auto 数据表(PDF) 68 Page - STMicroelectronics |
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ST72321R7-Auto 数据表(HTML) 68 Page - STMicroelectronics |
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68 / 243 page  Power saving modes ST72321xx-Auto 68/243 Doc ID 13829 Rev 1 Figure 28. Halt mode flowchart 1. WDGHALT is an option bit. See Section 21.1.1: Flash configuration on page 223 for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to Table 20: Interrupt mapping for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped. HALT INSTRUCTION RESET INTERRUPT (3) Y N N Y CPU OSCILLATOR PERIPHERALS (2) I[1:0] BITS OFF OFF 10 OFF FETCH RESET VECTOR OR SERVICE INTERRUPT CPU OSCILLATOR PERIPHERALS I[1:0] BITS ON OFF XX (4) ON CPU OSCILLATOR PERIPHERALS I[1:0] BITS ON ON XX (4) ON 256 OR 4096 CPU CLOCK DELAY WATCHDOG ENABLE DISABLE WDGHALT (1) 0 WATCHDOG RESET 1 (MCCSR.OIE = 0) CYCLE |
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