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ST72321R7-Auto 数据表(PDF) 46 Page - STMicroelectronics |
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ST72321R7-Auto 数据表(HTML) 46 Page - STMicroelectronics |
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46 / 243 page  Supply, reset and clock management ST72321xx-Auto 46/243 Doc ID 13829 Rev 1 Figure 16. Using the voltage detector to monitor the EVD pin (AVDS bit = 1) 6.6.3 Low power modes 6.6.4 Interrupts The AVD interrupt event generates an interrupt if the corresponding Enable Control Bit (AVDIE) is set and the interrupt mask in the CC register is reset (RIM instruction). VEVD VIT+(EVD) VIT-(EVD) AVDF 0 0 1 IF AVDIE = 1 Vhyst AVD INTERRUPT REQUEST INTERRUPT PROCESS INTERRUPT PROCESS Table 11. Effect of low power modes on SI Mode Effect Wait No effect on SI. AVD interrupts cause the device to exit from Wait mode. Halt The SICSR register is frozen. Table 12. AVD interrupt control/wake-up capability Interrupt event Event flag Enable control bit Exit from Wait Exit from Halt AVD event AVDF AVDIE Yes No |
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