ST72321R7-Auto datasheet(47/243 Pages) STMICROELECTRONICS

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ST72321xx-Auto

Supply, reset and clock management

Doc ID 13829 Rev 1

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6.6.5

System Integrity (SI) Control/Status register (SICSR)

SICSR

Reset value:

000x 000x (00h)

543

AVDS

AVDIE

AVDF

LVDRF

Reserved

WDGRF

Table 13.

SICSR description

Bit

Name

Function

7AVDS

Voltage Detection selection

This bit is set and cleared by software. Voltage Detection is available only if the

LVD is enabled by option byte.

0: Voltage detection on VDD supply

1: Voltage detection on EVD pin

AVDIE

Voltage Detector interrupt enable

This bit is set and cleared by software. It enables an interrupt to be generated

when the AVDF flag changes (toggles). The pending interrupt information is

automatically cleared when software enters the AVD interrupt routine.

0: AVD interrupt disabled

1: AVD interrupt enabled

5AVDF

Voltage Detector flag

This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an

interrupt request is generated when the AVDF bit changes value. Refer to

Figure 15 and to Monitoring the VDD main supply on page 44 for additional

details.

0: VDD or VEVD over VIT+(AVD) threshold

1: VDD or VEVD under VIT-(AVD) threshold

LVDRF

LVD reset flag

This bit indicates that the last Reset was generated by the LVD block. It is set by

hardware (LVD reset) and cleared by software (writing zero). See Table 14: Reset

source flags for more details. When the LVD is disabled by OPTION BYTE, the

LVDRF bit value is undefined.

3:1

Reserved, must be kept cleared.

WDGRF

Watchdog reset flag

This bit indicates that the last Reset was generated by the Watchdog peripheral. It

is set by hardware (watchdog reset) and cleared by software (writing zero) or an

LVD Reset (to ensure a stable cleared state of the WDGRF flag when CPU starts).

Combined with the LVDRF flag information, the flag description is given in

Table 14.

Reset source flags

Reset sources

LVDRF

WDGRF

External RESET pin

Watchdog

LVD

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