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ST72321R7-Auto 数据表(PDF) 96 Page - STMicroelectronics |
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ST72321R7-Auto 数据表(HTML) 96 Page - STMicroelectronics |
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96 / 243 page ![]() PWM auto-reload timer (ART) ST72321xx-Auto 96/243 Doc ID 13829 Rev 1 12.3.5 Duty cycle registers (PWMDCRx) A PWMDCRx register is associated with the OCRx register of each PWM channel to determine the second edge location of the PWM signal (the first edge location is common to all channels and given by the ARTARR register). These PWMDCR registers allow the duty cycle to be set independently for each PWM channel. 12.3.6 Input capture control / status register (ARTICCSR) PWMDCRx Reset value: 0000 0000 (00h) 76 543 21 0 DC[7:0] RW Table 52. PWMDCRx register description Bit Name Function 7:0 DC[7:0] Duty Cycle Data These bits are set and cleared by software. ARTICCSR Reset value: 0000 0000 (00h) 76 543 21 0 Reserved CS[2:1] CIE[2:1] CF[2:1] -RW RW RW Table 53. ARTICCSR register description Bit Name Function 7:6 - Reserved, always read as 0. 5:4 CS[2:1] Capture Sensitivity These bits are set and cleared by software. They determine the trigger event polarity on the corresponding input capture channel. 0: Falling edge triggers capture on channel x 1: Rising edge triggers capture on channel x 3:2 CIE[2:1] Capture Interrupt Enable These bits are set and cleared by software. They enable or disable the Input capture channel interrupts independently. 0: Input capture channel x interrupt disabled 1: Input capture channel x interrupt enabled 1:0 CF[2:1] Capture Flag These bits are set by hardware and cleared by software reading the corresponding ARTICRx register. Each CFx bit indicates that an input capture x has occurred. 0: No input capture on channel x 1: An input capture has occurred on channel x. |
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