ST72321R7-Auto datasheet(84/243 Pages) STMICROELECTRONICS

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Main clock controller with real-time clock and beeper (MCC/RTC)

ST72321xx-Auto

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Doc ID 13829 Rev 1

11.8

Main clock controller registers

11.8.1

MCC control/status register (MCCSR)

MCCSR

Reset value: 0000 0000 (00h)

543

MCO

CP[1:0]

SMS

TB[1:0]

OIE

OIF

Table 40.

MCCSR register description

Bit

Name

Function

7MCO

Main clock out selection

This bit enables the MCO alternate function on the PF0 I/O port. It is set and

cleared by software.

0: MCO alternate function disabled (I/O pin free for general-purpose I/O)

1: MCO alternate function enabled (fCPU on I/O port)

Note: To reduce power consumption, the MCO function is not active in Active Halt

mode.

6:5

CP[1:0]

CPU clock prescaler

These bits select the CPU clock prescaler which is applied in the different slow

modes. Their action is conditioned by the setting of the SMS bit. These two bits are

set and cleared by software.

00: fCPU in Slow mode = fOSC2/2

01: fCPU in Slow mode = fOSC2/4

10: fCPU in Slow mode = fOSC2/8

11: fCPU in Slow mode = fOSC2/16

4SMS

Slow mode select

This bit is set and cleared by software.

0: Normal mode. fCPU = fOSC2

1: Slow mode. fCPU is given by CP1, CP0

See Section 8.2: Slow mode on page 62 and Chapter 11: Main clock controller with

real-time clock and beeper (MCC/RTC) for more details.

3:2

TB[1:0]

Time base control

These bits select the programmable divider time base. They are set and cleared by

software (see Table 41).

A modification of the time base is taken into account at the end of the current period

(previously set) to avoid an unwanted time shift. This allows to use this time base

as a real-time clock.

1OIE

Oscillator interrupt enable

This bit set and cleared by software.

0: Oscillator interrupt disabled

1: Oscillator interrupt enabled

This interrupt can be used to exit from Active Halt mode.

When this bit is set, calling the ST7 software HALT instruction enters the Active Halt

power saving mode.

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