STM32F769AI datasheet(152/255 Pages) STMICROELECTRONICS

152 / 255 page

Electrical characteristics

STM32F765xx STM32F767xx STM32F768Ax STM32F769xx

152/255

DocID029041 Rev 4

VIL

Output low level voltage

1.1

1.2

VIL-ULPS

Output high level voltage

-50

VIH

Output impedance of LP

transmitter

-110

Vhys

15%-85% rise and fall time

LP Contention Detector Characteristics

VILCD

Logic 0 contention threshold

200

VIHCD

Logic 0 contention threshold

450

1. Guaranteed based on test during characterization.

Table 52. MIPI D-PHY AC characteristics LP mode and HS/LP

transitions(1)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

TLPX

Transmitted length of any Low-

Power state period

-50

TCLK-PREPARE

Time that the transmitter drives

the Clock Lane LP-00 Line

state immediately before the

HS-0 Line state starting the HS

transmission.

-38

TCLK-PREPARE

TCLK-ZERO

Time that the transmitter drives

the HS-0 state prior to starting

the clock.

300

TCLK-PRE

Time that the HS clock shall be

driven by the transmitter prior to

any associated Data Lane

beginning the transition from

LP to HS mode.

-8

Table 51. MIPI D-PHY characteristics(1) (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

STM32F769AI 数据表(PDF) 152 Page - STMicroelectronics

STM32F769AI 数据表(HTML) 152 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载