STM32F769AI datasheet(212/255 Pages) STMICROELECTRONICS

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Electrical characteristics

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SDRAM waveforms and timings

•

CL = 30 pF on data and address lines. CL = 10 pF on FMC_SDCLK unless otherwise

specified.

In all timing tables, the THCLK is the HCLK clock period.

–

For 3.0 V≤ VDD≤ 3.6 V, maximum FMC_SDCLK = 100 MHz at CL=20 pF (on FMC_SDCLK).

–

For 2.7 V≤ VDD≤ 3.6 V, maximum FMC_SDCLK = 90 MHz at CL=30 pF (on FMC_SDCLK).

–

For 1.71 V≤ VDD<1.9 V, maximum FMC_SDCLK = 70 MHz at CL=10 pF (on FMC_SDCLK).

Figure 73. SDRAM read access waveforms (CL = 1)

Table 113. Switching characteristics for NAND Flash write cycles(1)

1. Guaranteed by characterization results.

Symbol

Parameter

Min

Max

Unit

tw(NWE)

FMC_NWE low width

4THCLK 0.5 4THCLK + 0.5

tv(NWE-D)

FMC_NWE low to FMC_D[15-0] valid

th(NWE-D)

FMC_NWE high to FMC_D[15-0] invalid

2THCLK 1-

td(D-NWE)

FMC_D[15-0] valid before FMC_NWE high

5THCLK 1-

td(ALE-NWE)

FMC_ALE valid before FMC_NWE low

3THCLK + 1

th(NWE-ALE)

FMC_NWE high to FMC_ALE invalid

2THCLK 2-

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