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TP3420AV 数据表(PDF) 25 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部件名 TP3420AV
功能描述  ISDN S/T Interface Device
PDF  32 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  NSC [National Semiconductor (TI)]
网页  http://www.national.com
标志 NSC - National Semiconductor (TI)

TP3420AV 数据表(HTML) 25 Page - National Semiconductor (TI)

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Timing Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Units
MCLK SYSTEM CLOCK (See
Figure 5)
F
MCK
Master Clock Frequency
15.36
MHz
Master Clock Tolerance
−100
+100
ppm
MCLK/XTAL Input Clock Jitter
External Clock Source
50
ns pk-pk
t
MH,
Clock Pulse Width
V
IH = VCC − 0.5V
20
ns
t
ML
Hi & Low for MCLK
V
IL = 0.5V
t
MR,
Rise and Fall Time
Used as a
10
ns
t
MF
of MCLK
Logic Input
MICROWIRE CONTROL INTERFACE (See
Figure 5)
t
CH
CCLK High Duration
50
ns
t
CL
CCLK Low Duration
50
ns
t
SIC
Setup Time, CI
30
ns
Valid to CCLK Edge
t
HCI
Hold Time, CCLK
20
ns
High to CI Invalid
t
DCSO
Delay Time from CS
Bit C7 only
50
ns
Low to CO Valid
t
DCO
Delay Time from CCLK Edge
50
ns
to CO Data Valid
t
DCSZ
Delay Time from CS High
30
ns
to CO TRI-STATE
t
SCSC1
Setup Time, from CS Low to
30
ns
CCLK Edge High
t
HCSC1
Hold Time, CS High from
40
ns
CCLK Edge High
t
HCSC2
Hold Time, CS Low from
50
ns
CCLK Edge High
t
SCSC2
Setup Time, CS High
50
ns
to CCLK Edge High
t
CSH
Duration of CS High
1µs
t
DCI
Delay Time CS Low to
250
ns
INT High-impedance
DIGITAL SYSTEM INTERFACE (See
Figure 9)
F
BCK
Bit Clock Frequency
256
4096
kHz
t
BH,
Clock Pulse Width
V
IH = 2.2V
60
ns
t
BL
Hi & Low for BCLK
V
IL = 0.7V
t
BR,
Rise and Fall Time
15
ns
t
BF
of BCLK
t
FSa/b
Frame Sync Frequency
8
kHz
t
SBC
Set up Time, B
x Valid
All Modes
30
ns
to BCLK Low
t
HCB
Hold Time, B
x Valid
All Modes
20
ns
from BCLK Low
t
DCD
Delay Time, BCLK Transition
TEM, DCKE Mode
0
40
ns
to DTCK Transition
t
SDT
Setup Time, TxD Valid to
TEM, DCKE Mode
30
ns
BCLK Low
t
HDT
Hold Time, BCLK Low to TxD
Invalid
TEM, DCKE Mode
20
ns
www.national.com
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