TP3420AV datasheet(3/32 Pages) NSC

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Pin Descriptions (Continued)

Name

Description

In NT modes and TES mode, this pin is

the Transmit Frame Sync pulse

TTL/CMOS input, requiring a positive

edge to indicate the start of the active

channel time for transmit “B” and “D”

channel data into B

x. In TEM mode only,

this pin is a digital output pulse whose

positive indicates the start of the “B”

channel data transfer at both B

x and Br.

(Pin 11)

In NT modes and TES mode, this pin is

the Receive Frame Sync pulse

TTL/CMOS input, requiring a positive

edge to indicate the start of the active

channel time of the device for receive “B”

and “D” channel data out from B

r.InTEM

mode only, when digital interface Format

1 is selected, this pin is an 8-bit wide

pulse which indicates the active slot for

the B2 channel on the digital interface.

The DCKE command will alter the

function of this pin. See

Table 2 for

details.

TTL/CMOS input for “B” and “D” channel

data to be transmitted to the line; must be

synchronous with BCLK.

CMOS output for “B” and “D” channel

data received from the line, which is

synchronous with BCLK. When not

shifting data, this pin is TRI-STATE®.

DEN

x/p2

(Pin 8)

In TEM mode, this pin by default is a

CMOS output which is normally low and

pulses high to indicate the active bit-times

for “D” channel Transmit data at the B

input. It is intended to be gated with

BCLK to control the shifting of data from

layer 2 device to the TP3420A transmit

buffer.

In NT modes, this pin by default is a

pulse output (DEN

x) which occurs in

every 8 KHz frame and indicates the

location of D channel data input on the B

pin.

In TES mode, this pin by default is an

output synchronized clock (SCLK) at the

frequency selected by the Digital

Interface Format. This clock is

phase-locked to the received line signal,

and is intended to be used as the BCLK

source.

This pin called P2 in

Table 1 can also be

programmed to provide alternate

functions. See

Table 1 for details.

MICROWIRE control channel serial data

TTL/CMOS input.

Name

Description

Control channel serial data CMOS output

for status information. When not enabled

by CS, this output is TRI-STATE.

CCLK

TTL/CMOS clock input for the Control

Channel.

Chip Select input which enables the

control channel data to be shifted in and

out when pulled low. When high, this pin

inhibits the Control interface.

INT

Interrupt output, a latched n-channel

open-drain output signal which is

normally high impedance, and goes low

to indicate a change of status of the loop

transmission system.

LSD/P1

(Pin 18)

In all modes, this pin by default is the

Line Signal Detect output, an n-channel

open-drain output which is normally

high-impedance, but pulls low when the

device is powered down and a received

line signal is detected. It is intended to be

used to “wake-up” a microprocessor from

a low-power idle mode. This output is

high impedance when the device is

powered up.

This pin P1 in

Table 1 can also be

programmed to provide alternate

functions. See

Table 1 for details.

o+, Lo−

Transmit AMI signal differential outputs to

the line transformer. When used with a

2:1 step-down transformer, the line signal

conforms to the output pulse masks in

I.430.

i+, Li−

Receive AMI signal differential inputs

from the line transformer. The L

i− pin is

also the internal voltage reference pin,

and must be decoupled to GND with a 10

µf capacitor in parallel with a 0.1 µF

ceramic capacitor.

Note 1: Crystal specification: 15.36 MHz parallel resonant; Rs ≤ 150Ω,

CL = 20 pF and CO < 7pF.

Note 2: The 33 pF includes any board capacitance.

ALTERNATE PIN FUNCTIONS

With a MICROWIRE command PINDEF (B'1110 0 x2 x1 x0)

the pin signal functions of these pins can be changed to pro-

vide alternate functions (see

Table 1 and the MICROWIRE

command in

Table 4). “*” indicates the default pin function af-

ter a device mode selection. Power-up default device mode

is NTA.

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