TP3420AV datasheet(21/32 Pages) NSC

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Functional Description (Continued)

BIPOLAR VIOLATION DETECTION AND FECV

MESSAGING VIA THE SC1 CHANNEL

NT Mode

A Receive Multiframe Error (RMFE) detector circuit in the

TP3420A identifies any multiframes in which one or more bi-

polar violations is received, indicating a bit in error. If one or

more line code violation errors occur in a received multi-

frame (5 ms), the TP3420A generates the RMFE (Receive

Multiframe Error) interrupt. The microcontroller has to send

the Far End Code Violation, FECV (1110) word over the SC1

channel through the MFT1H register. The FECV message is

then sent once, after which the SC1 channel reverts to send-

ing the message from the MFT1L register.

The RMFE circuit detects frame code violations in 16 frames

(out of 20 frames in the multiframe) not containing the multi-

frame Q bit data and detects correct DC balancing in all 20

frames, including the frames containing the multiframe data.

The RMFE detector is operational whether multiframing

messaging is used or not. The RMFE interrupt is disabled by

default on power-up. It is normally enabled after activation is

completed by writing the ENINT command.

TE Mode

When the TE end device receives an FECV message in the

SC1 channel, it is validated on a single occurrence, and the

device generates the MFR1.

If one or more line code violation errors occur in the received

multiframe, the device will generate the RMFE interrupt. The

microcontroller may then keep a count of frame errors being

received. Currently, there is no provision in T1-605 for in-

forming the NT about the errors received at the TE end.

The RMFE circuit detects frame code violations as well as

DC balancing in all 20 frames in the multiframe. In the TE re-

ceived frames, the S bit (for SC1, SC2, etc.) is independent

of the auxiliary framing pulses. The RMFE detector is opera-

tional whether multiframing messaging is used or not. The

RMFE interrupt is disabled by default on power-up. It is nor-

mally enabled after activation is completed by writing the

ENINT command.

Applications Information

While the pins of the TP3420A SID are well protected

against electrical misuse, it is recommended that the stan-

dard CMOS practice of applying GND to the device before

any other connections are made should always be followed.

In applications where the printed circuit card may be plugged

into a hot socket with power and clocks already present, an

extra long ground pin on the connector should be used.

To minimize noise sources, all ground connections to each

device should meet at a common point as close as possible

to the GND pin in order to prevent the interaction of ground

return currents flowing through a common bus impedance. A

decoupling capacitor of 0.1 µF should be connected from

this common point to V

CC. Taking care with the pcb layout in

the following ways will help prevent noise injection into the

receiver front-end and maximize the transmission perfor-

mance:

keep the crystal oscillator components away from the re-

ceiver inputs and use a shielded ground plane around

these components.

keep the connections between the device and the com-

ponents on the L

i±

inputs short; the L

i−

capacitors

should be connected close to the device pins.

keep the connections between the device and the trans-

formers short.

Figure 6 shows a typical application of the TP3420A in an

ISDN Terminal.

For more in-depth information on a variety of applications,

Application Note AN665 is a comprehensive guide to the

hardware and software required to meet the I.430 interface

specification. Performance measurements, demonstrating

compliance with I.430 and ANSI transmission requirements,

are also included. For additional information on firmware for

the maintenance message channels see Appendix A of this

datasheet.

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