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TP3420AV 数据表(PDF) 26 Page - National Semiconductor (TI) |
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TP3420AV 数据表(HTML) 26 Page - National Semiconductor (TI) |
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26 / 32 page  Timing Characteristics (Continued) Symbol Parameter Conditions Min Typ Max Units DIGITAL SYSTEM INTERFACE (See Figure 9) t HCFH Hold Time, BCLK High NT and TES Modes 0 ns to FS a and FSb High (Inputs) only t SFC Set up Time, FS a and NT and TES Modes 50 ns FSb Inputs to BCLK Low only t HCFL Hold Time, BCLK Low NT and TES Modes 20 ns to FS a and FSb Low (Inputs) only t DBFR Delay Time, FS b Input NT and TES Modes, 80 ns to B r Valid Bit 1 only t DBF Delay Time, BCLK High TEM mode only 50 ns to FS a and FSb Transitions (Outputs) t DCB Delay Time, BCLK All Modes 80 ns High to Data Valid t DCBZ Delay Time, BCLK Low All Modes 10 120 ns to Data Invalid (Last Bit Only) (Note 28) t DCD Delay Time, BCLK TEM Mode only 40 ns High to DEN x Transition Note 28: This parameter can be extended by connecting a 10 k Ω pull-up resistor and a 10 pf pull-down capacitor to Br. Timing Diagrams DS009143-9 FIGURE 9. Timing Details for Digital System Interface www.national.com 26 |
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