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DOC4106 数据表(PDF) 32 Page - ATMEL Corporation |
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DOC4106 数据表(HTML) 32 Page - ATMEL Corporation |
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32 / 47 page  32 AT8xC51SND1C 4106F–8051–10/02 Table 43. External IDE 16-bit Bus Cycle – Data Read AC Timings VDD = 2.7 to 3.3V, TA =-40° to +85°C Table 44. External IDE 16-bit Bus Cycle – Data Write AC Timings VDD =2.7 to 3.3V, TA =-40° to +85°C Symbol Parameter Variable Clock Standard Mode Variable Clock X2 Mode Unit Min Max Min Max T CLCL Clock Period 50 50 ns T LHLL ALE Pulse Width 2·T CLCL-15 T CLCL-15 ns T AVLL Address Valid to ALE Low T CLCL-20 0.5·T CLCL-20 ns T LLAX Address Hold after ALE Low T CLCL-20 0.5·T CLCL-20 ns T LLRL ALE Low to RD Low 3·T CLCL-30 1.5·T CLCL-30 ns T RLRH RD Pulse Width 6·T CLCL-25 3·T CLCL-25 ns T RHLH RD High to ALE High T CLCL-20 T CLCL+20 0.5·T CLCL-20 0.5·T CLCL+20 ns T AVDV Address Valid to Valid Data In 9·T CLCL-65 4.5·T CLCL-65 ns T AVRL Address Valid to RD Low 4·T CLCL-30 2·T CLCL-30 ns T RLDV RD Low to Valid Data 5·T CLCL-30 2.5·T CLCL-30 ns T RLAZ RD Low to Address Float 0 0 ns T RHDX Data Hold after RD High 0 0 ns T RHDZ Instruction Float after RD High 2·T CLCL-25 T CLCL-25 ns Symbol Parameter Variable Clock Standard Mode Variable Clock X2 Mode Unit Min Max Min Max TCLCL Clock Period 50 50 ns TLHLL ALE Pulse Width 2·TCLCL-15 TCLCL-15 ns TAVLL Address Valid to ALE Low TCLCL-20 0.5·TCLCL-20 ns TLLAX Address Hold after ALE Low TCLCL-20 0.5·TCLCL-20 ns TLLWL ALE Low to WR Low 3·TCLCL-30 1.5·TCLCL-30 ns TWLWH WR Pulse Width 6·TCLCL-25 3·TCLCL-25 ns TWHLH WR High to ALE High TCLCL-20 TCLCL+20 0.5·TCLCL-20 0.5·TCLCL+20 ns TAVWL Address Valid to WR Low 4·TCLCL-30 2·TCLCL-30 ns TQVWH Data ValidtoWR High 7·TCLCL-20 3.5·TCLCL-20 ns TWHQX Data Hold after WR High TCLCL-15 0.5·TCLCL-15 ns |
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