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DOC4106 数据表(PDF) 34 Page - ATMEL Corporation |
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DOC4106 数据表(HTML) 34 Page - ATMEL Corporation |
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34 / 47 page  34 AT8xC51SND1C 4106F–8051–10/02 Timings Table 46. SPI Interface Master AC Timing (2) VDD =2.7 to 3.3V, TA =-40° to +85°C Notes: 1. Value of this parameter depends on software. 2. Test conditions: capacitive load on all pins = 100 pF Symbol Parameter Min Max Unit Slave Mode TCHCH Clock Period 8 TOSC TCHCX Clock High Time 3.2 TOSC TCLCX Clock Low Time 3.2 TOSC TSLCH,TSLCL SS Low to Clock edge 200 ns TIVCL,TIVCH Input Data Valid to Clock Edge 100 ns TCLIX,TCHIX Input Data Hold after Clock Edge 100 ns TCLOV, TCHOV Output Data Valid after Clock Edge 100 ns TCLOX,TCHOX Output Data Hold Time after Clock Edge 0 ns TCLSH,TCHSH SS High after Clock Edge 0 ns TIVCL,TIVCH Input Data Valid to Clock Edge 100 ns TCLIX,TCHIX Input Data Hold after Clock Edge 100 ns TSLOV SS Low to Output Data Valid 130 ns TSHOX Output Data Hold after SS High 130 ns TSHSL SS High to SS Low Note (1) TILIH Input Rise Time 2 µs TIHIL Input Fall Time 2 µs TOLOH Output Rise Time 100 ns TOHOL Output Fall Time 100 ns Master Mode TCHCH Clock Period 4 TOSC TCHCX Clock High Time 1.6 TOSC TCLCX Clock Low Time 1.6 TOSC TIVCL,TIVCH Input Data Valid to Clock Edge 50 ns TCLIX,TCHIX Input Data Hold after Clock Edge 50 ns TCLOV, TCHOV Output Data Valid after Clock Edge 65 ns TCLOX,TCHOX Output Data Hold Time after Clock Edge 0 ns TILIH Input DataRiseTime 2 µs TIHIL Input Data Fall Time 2 µs TOLOH Output Data Rise Time 50 ns TOHOL Output Data Fall Time 50 ns |
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