TMS320DM6431 datasheet(30/227 Pages) TI1

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TMS320DM6431

Digital Media Processor

SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008

www.ti.com

Table 2-10. EMIFA Terminal Functions (EMIFA Pinout Mode 1, AEM[2:0] = 001) (continued)

SIGNAL

TYPE(1)

OTHER(2)(3)

DESCRIPTION

ZWT

ZDU

NAME

NO.

This pin is multiplexed between VPFE (CCDC), EMIFA, and GPIO.

C_FIELD/

IPD

D12

C16

I/O/Z

EM_A[21]/GP[34]

DVDD33

For EMIFA, it is address bit 21 output EM_A[21].

This pin is multiplexed between VPFE (CCDC), EMIFA, and GPIO.

CI0(CCD8)/

IPD

C12

C15

I/O/Z

For EMIFA (AEM[2:0] = 001), this pin is address bit 20 output

EM_A[20]/GP[44]

DVDD33

EM_A[20] if AEAW[2:0] = 100b.

This pin is multiplexed between VPFE (CCDC), EMIFA, and GPIO.

CI1(CCD9)/

IPD

B12

C14

I/O/Z

For EMIFA (AEM[2:0] = 001), this pin is address bit 19 output

EM_A[19]/GP[45]

DVDD33

EM_A[19] if AEAW[2:0] = 100b.

This pin is multiplexed between EMIFA and GPIO.

IPD

EM_A[18]/GP[46]

D11

A14

I/O/Z

For EMIFA (AEM[2:0] = 001), this pin is address bit 18 output

DVDD33

EM_A[18] if AEAW[2:0] = 011/100b.

This pin is multiplexed between EMIFA and GPIO.

IPD

EM_A[17]/GP[47]

A11

B14

I/O/Z

For EMIFA (AEM[2:0] = 001), this pin is address bit 17 output

DVDD33

EM_A[17] if AEAW[2:0] = 011/100b.

This pin is multiplexed between EMIFA and GPIO.

IPD

EM_A[16]/GP[48]

C11

B13

I/O/Z

For EMIFA (AEM[2:0] = 001), this pin is address bit 16 output

DVDD33

EM_A[16] if AEAW[2:0] = 010/011/100b.

This pin is multiplexed between EMIFA and GPIO.

IPD

EM_A[15]/GP[49]

B11

C13

I/O/Z

For EMIFA (AEM[2:0] = 001), this pin is address bit 15 output

DVDD33

EM_A[15] if AEAW[2:0] = 010/011/100b.

This pin is multiplexed between EMIFAand GPIO.

IPD

EM_A[14]/GP[50]

A10

A13

I/O/Z

For EMIFA (AEM[2:0] = 001), this pin is address bit 14 output

DVDD33

EM_A[14] if AEAW[2:0] = 001/010/011/100b.

This pin is multiplexed between EMIFA and GPIO.

IPD

EM_A[13]/GP[51]

B10

A12

I/O/Z

For EMIFA (AEM[2:0] = 001), this pin is address bit 13 output

DVDD33

EM_A[13] if AEAW[2:0] = 001/010/011/100b.

This pin is multiplexed between EMIFA and GPIO.

IPD

EM_A[12]/GP[89]

D10

B12

I/O/Z

DVDD33

For EMIFA, this pin is address bit 12 output EM_A[12].

This pin is multiplexed between EMIFA and GPIO.

IPD

EM_A[11]/GP[90]

C10

C12

I/O/Z

DVDD33

For EMIFA, this pin is address bit 11 output EM_A[11].

This pin is multiplexed between EMIFA and GPIO.

IPD

EM_A[10]/GP[91]

B11

I/O/Z

DVDD33

For EMIFA, this pin is address bit 10 output EM_A[10].

This pin is multiplexed between EMIFA and GPIO.

IPD

EM_A[9]/GP[92]

C11

I/O/Z

DVDD33

For EMIFA, this pin is address bit 9 output EM_A[9].

This pin is multiplexed between EMIFA and GPIO.

IPD

EM_A[8]/GP[93]

A11

I/O/Z

DVDD33

For EMIFA, this pin is address bit 8 output EM_A[8].

This pin is multiplexed between EMIFA and GPIO.

IPD

EM_A[7]/GP[94]

C10

I/O/Z

DVDD33

For EMIFA, this pin is address bit 7 output EM_A[7].

This pin is multiplexed between EMIFA and GPIO.

IPD

EM_A[6]/GP[95]

B10

I/O/Z

DVDD33

For EMIFA, this pin is address bit 6 output EM_A[6].

This pin is multiplexed between EMIFA and GPIO.

IPD

EM_A[5]/GP[96]

A10

I/O/Z

DVDD33

For EMIFA, this pin is address bit 5 output EM_A[5].

This pin is multiplexed between EMIFA and GPIO.

EM_A[4]/GP[10]/

IPD

A17

B21

I/O/Z

(AEAW2/PLLMS2)

DVDD33

For EMIFA, this pin is address bit 4 output EM_A[4].

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