TMS320DM6431 datasheet(75/227 Pages) TI1

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3.5.1.1 EMIFA Pinout Mode (AEM[2:0])

3.5.1.2 EMIFA Address Width Select (AEAW) and FASTBOOT PLL Multiplier Select (PLLMS)

3.6 Configurations After Reset

TMS320DM6431

Digital Media Processor

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SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008

The following subsections provide more details on the device configurations determined at device reset:

AEM and AEAW/PLLMS.

To support different usage scenarios, the DM6431 provides intricate pin multiplexing between the EMIFA

and other peripherals. The PINMUX0.AEM register bit field in the System Module determines the EMIFA

Pinout Mode. The AEM[2:0] pins only select the default EMIFA Pinout Mode. It is latched at device reset

de-assertion (high) into the BOOTCFG.DAEM bit field. The AEM[2:0] value also sets the default of the

PINMUX0.AEM bit field. While the BOOTCFG.DAEM bit field shows the actual latched value and cannot

be modified, the PINMUX0.AEM value can be changed by software to modify the EMIFA Pinout Mode.

Note: The AEM[2:0] value does not affect the operation of the EMIFA module itself. It only affects which

EMIFA pins are brought out to the device pins. For more details on the AEM settings, see Section 3.7,

Multiplexed Pin Configurations.

In addition, for Fastboot modes (FASTBOOT = 1), the bootloader code determines the PLL1 multiplier

based on the default settings of AEM[2:0] and PLLMS[2:0]. For more details, see Section 3.4.1.1,

Fastboot, and Section 3.5.1.2, EMIFA Address Width Select (AEAW) and FASTBOOT PLL Multiplier

Select (PLLMS).

The AEAW[2:0]/PLLMS[2:0] pins serve two functional purposes (AEAW or PLLMS), depending on the

FASTBOOT and AEM settings. The AEAW[2:0]/PLLMS[2:0] pins are latched at device reset de-assertion

(high) and captured in the BOOTCFG.PLLMS bit field. This value also sets the default of the

PINMUX0.AEAW field.

While the BOOTCFG.PLLMS field shows the actual latched value and cannot be modified, the

PINMUX0.AEAW value can be changed by software to modify the EMIFA pinout.

AEAW as EMIFA Address Width Select (AEAW)

If AEM[2:0] = 001b [8-bit EMIFA (Async) Pinout Mode 1], the AEAW[2:0]/PLLMS[2:0] pins serve as AEAW

to set the default of the EMIFA Address Width Selection.

When EMIFA is used in the 8-bit EMIFA (Async) Pinout Mode 1 (PINMUX0.AEM = 001b), the user has the

option to determine how many address pins are needed. The unused address pins can be used as

general-purpose input/output (GPIO) pins or extra data pins for VPFE. For more details on how the AEAW

settings control the exact pin out when AEM = 001b, see Section 3.7.3.11, EMIFA/VPSS Block Muxing.

For other EMIFA Pinout Modes (AEM not 001b), AEAW is not applicable in determining the EMIFA

address width.

Note: AEAW[2:0] value does not affect the operation of the EMIFA module itself. It only affects which of

the EMIFA address bits are brought out to the device pins.

AEAW as Fast Boot PLL Multiplier Select (PLLMS)

If FASTBOOT = 1, and AEM[2:0] = 000b [No EMIFA] or 101b [8-bit EMIFA (NAND) Pinout Mode 5], the

AEAW[2:0]/PLLMS[2:0] pins serve as PLLMS to select PLL multiplier for Fastboot modes.

For more information on boot modes and the FASTBOOT PLL multiplier selection, see Section 3.4.1, Boot

Modes.

The following sections provide details on configuring the device after reset.

Multiplexed pins are configured both at and after reset. Section 3.5.1, Device and Peripheral

Configurations at Device Reset, discusses multiplexed pin control at reset. For more details on multiplexed

pins control after reset, see Section 3.7 , Multiplexed Pin Configurations.

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