TMS320DM6431 datasheet(61/227 Pages) TI1

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TMS320DM6431

Digital Media Processor

www.ti.com

SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008

Table 3-2. VDD3P3V_PWDN Register Bit Descriptions (continued)

BIT

NAME

DESCRIPTION

UART0 Data Block I/O Power Down Control.

Controls the power of the 2 I/O pins in the UART0 Data Block.

UR0DAT

0 = I/O pins powered up.

1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z) [default].

Timer1 Block I/O Power Down Control.

Controls the power of the 2 I/O pins in the Timer1 Block.

TIMER1

0 = I/O pins powered up.

1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z) [default].

Timer0 Block I/O Power Down Control.

Controls the power of the 2 I/O pins in the Timer0 Block.

TIMER0

0 = I/O pins powered up.

1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z) [default].

Serial Port Block I/O Power Down Control.

Controls the power of the 12 I/O pins in the Serial Port Block (Serial Port Sub-Block 0 and

Serial Port Sub-Block 1).

0 = I/O pins powered up.

1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z) [default].

PWM1 Block I/O Power Down Control.

Contros thel power of the 1 I/O pin in the PWM1 Block.

PWM1

0 = I/O pins powered up.

1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z) [default].

GPIO Block I/O Power Down Control.

Controls the power of the 4 I/O pins in the GPIO Block (GP[3:0]).

Note: The GPIO Block contains standalone GPIO pins and is not a pin mux group.

GPIO