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TMS320DM6431 数据表(PDF) 63 Page - Texas Instruments

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部件名 TMS320DM6431
功能描述  Digital Media Processor
PDF  227 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

TMS320DM6431 数据表(HTML) 63 Page - Texas Instruments

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3.3.2
VPSS Clocks
3.4 Boot Sequence
TMS320DM6431
Digital Media Processor
www.ti.com
SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008
Table 3-3. DM6431 Default Module States (continued)
DEFAULT MODULE STATE
LPSC #
MODULE NAME
[PSC Register MDSTATn.STATE]
13
DDR2 Memory Contoller
SwRstDisable
SwRstDisable, if configuration pins AEM[2:0] = 000b
14
EMIFA
Enable, if configuration pins AEM[2:0] = Others [001b and 101b]
16
McBSP0
SwRstDisable
18
I2C
SwRstDisable
19
UART0
SwRstDisable
22
HECC
SwRstDisable
23
PWM0
SwRstDisable
24
PWM1
SwRstDisable
25
PWM2
SwRstDisable
26
GPIO
SwRstDisable
27
TIMER0
SwRstDisable
28
TIMER1
SwRstDisable
39
C64x+ CPU
Enable
The Video Processing SubSystem (VPSS) clocks are controlled via the VPSS_CLKCTL register. The
VPSS_CLKCTL register format is shown in Figure 3-2 and the bit field descriptions are given in Table 3-4.
31
16
RESERVED
R-0000 0000 0000 0000
15
5
4
3
2
1
0
PCLK
RESERVED
RESERVED
RESERVED
INV
R-0000 0000 000
R/W-00
R/W-0
R/W-00
LEGEND: R = Read; W = Write; -n = value after reset
Figure 3-2. VPSS_CLKCTL Register— 0x01C4 0044
Table 3-4. VPSS_CLKCTL Register Description
BIT
NAME
DESCRIPTION
31:5
RESERVED
Reserved. Read-only, writes have no effect.
Reserved. For proper device operation, the user must only write "0" to these
4:3
RESERVED
bits.
PCLK polarity
2
PCLKINV
0 = VPSS receives normal PCLK [default].
1 = VPSS receives inverted PCLK.
Reserved. For proper device operation, the user must only write "0" to these
1:0
RESERVED
bits.
The boot sequence is a process by which the device's memory is loaded with program and data sections,
and by which some of the device's internal registers are programmed with predetermined values. The boot
sequence is started automatically after each device-level global reset. For more details on device-level
global resets, see Section 6.5, Reset.
Submit Documentation Feedback
Device Configurations
63



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