TMS320DM6431 datasheet(79/227 Pages) TI1

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3.7 Multiplexed Pin Configurations

TMS320DM6431

Digital Media Processor

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SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008

Table 3-17. EDMATCCFG Register Description (continued)

Bit

Field

Description

EDMA TC1 Default Burst Size

00 = 16 byte

01 = 32 byte (default)

10 = 64 byte

3:2

TC1DBS

11 = reserved

EDMA TC1 is intended for high throughput bulk transfers.

TC1 FIFO size is 256 bytes, regardless of Default Burst Size setting.

EDMA TC0 Default Burst Size

00 = 16 byte (default)

01 = 32 byte

10 = 64 byte

1:0

TC0DBS

11 = reserved

EDMA TC0 is intended for short burst transfers with stringent deadlines (e.g., McBSP, McASP).

TC0 FIFO size is 128 bytes, regardless of Default Burst Size setting.

DM6431 makes extensive use of pin multiplexing to accommodate a large number of peripheral functions

in the smallest possible package, providing ultimate flexibility for end applications.

The Pin Multiplex Registers PINMUX0 and PINMUX1 in the System Module are responsible for controlling

all pin multiplexing functions on the DM6431. The default setting of some of the PINMUX0 and PINMUX1

bit fields are configured by configuration pins latched at reset (see Section 3.5.1, Device and Peripheral

Configurations at Device Reset). After reset, software may program the PINMUX0 and PINMUX1 registers

to switch pin functionalities.

The following peripherals have multiplexed pins: VPSS (VPFE), EMIFA, EMAC, McASP0, McBSP0,

PWM0, PWM1, PWM2, Timer0, Timer1, UART0, HECC, and GPIO.

The device is divided into the following Pin Multiplexed Blocks (Pin Mux Blocks):

• EMIFA/VPSS Block: VPSS (VPFE), EMIFA, and GPIO. This block is further subdivided into these

sub-blocks:

–

Sub-Block 0: VPFE (CCDC), part of EMIFA (address and control), and GPIO

–

Sub-Block 1: part of EMIFA (data, address, control), and GPIO

–

Sub-Block 2: part of EMIFA (control signals EM_WAIT/(RDY/BSY), EM_OE, and EM_WE)

–

Sub-Block 3: part of EMIFA (address EM_A[12:5]), and GPIO

• Host Block: EMAC and GPIO

• Serial Port Block: McBSP0, McASP0, and GPIO. This block is further sub-divided into sub-blocks.

–

Serial Port Sub-Block 0: McBSP0, part of McASP0, and GPIO

–

Serial Port Sub-Block 1: part of McASP0 and GPIO

• UART0 Flow Control Block: UART0 flow control, PWM0, and GPIO

• UART0 Data Block: UART0 data and GPIO

• Timer0 Block: Timer0 and McBSP0 CLKS pins

• Timer1 Block: Timer1 and HECC

• PWM1 Block: PWM1 and GPIO

• CLKOUT Block: CLKOUT0, PWM2, and GPIO

As shown in the list above, the McBSP0 and UART0 peripherals span multiple Pin Mux Blocks. To use

these peripherals, they must be selected in all relevant Pin Mux Blocks. For more details, see

Section 3.7.3, Pin Multiplexing Details, and Section 3.7.3.2, Peripherals Spanning Multiple Pin Mux

Blocks.

Note: There is no actual pin multiplexing in EMIFA/VPSS Sub-Block 2. However, this is still considered a

"pin mux block" because it contains part of the pins necessary for EMIFA.

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