TMS320DM6431 datasheet(67/227 Pages) TI1

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TMS320DM6431

Digital Media Processor

www.ti.com

SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008

Table 3-7. User-Select Multiplier Fastboot Modes (FASTBOOT = 1, AEM[2:0] = 000b or 101b)

DEVICE BOOT AND

CONFIGURATION

PLLC1 CLOCK SETTING AT BOOT

PINS

DM6431 DMP

DSPBOOTADDR

BOOT DESCRIPTION(1)

(Master/Slave)

(DEFAULT)(1)

DEVICE

PLL

CLKDIV1 DOMAIN

BOOTMODE[3:0]

FREQUENCY

MODE(2)

(SYSCLK1 DIVIDER)

(SYSCLK1)

0000

No Boot (Emulation Boot)

Master

Bypass

CLKIN

0x0010 0000

0001

Reserved

–

0010

Reserved

–

0011

Reserved

–

EMIFA ROM FASTBOOT

0100

Master

Table 3-8

0x0010 0000

with AIS

I2C Boot

0101

Master

Table 3-8

0x0010 0000

[FAST MODE](3)

0110

16-bit SPI Boot [McBSP0]

Master

Table 3-8

0x0010 0000

0111

NAND Flash Boot

Master

Table 3-8

0x0010 0000

UART Boot without

1000

Hardware Flow Control

Master

Table 3-8

0x0010 0000

[UART0]

EMIFA ROM FASTBOOT

1001

Master

Table 3-8

–

without AIS

1010

Reserved

–

1011

Reserved

–

1100

Reserved

–

1101

Reserved

–

UART Boot with Hardware

1110

Master

Table 3-8

0x0010 0000

Flow Control [UART0]

1111

Reserved

–

(1)

For all boot modes that default to DSPBOOTADDR = 0x0010 0000, the bootloader code disables all C64x+ cache (L2, L1P, and L1D)

so that upon exit from the bootloader code, all C64x+ memories are configured as all RAM. If cache use is required, the application

code must explicitly enable the cache. For more information on the bootloader, see the Using the TMS320DM643x Bootloader

Application Report (literature number SPRAAG0).

(2)

Any supported PLL MODE is available. [See Table 3-8 for supported DM6431 PLL MODE options].

(3)

I2C Boot (BOOTMODE[3:0] = 0101b) is only available if the MXI/CLKIN frequency is between 21 MHz to 30 MHz. I2C Boot is not

available for MXI/CLKIN frequencies less than 21 MHz.

Table 3-8. PLL Multiplier Selection (PLLMS[2:0]) in User-Select Multiplier Fastboot Modes

(FASTBOOT = 1; AEM[2:0] = 000b or 101b)

DEVICE BOOT AND

PLLC1 CLOCK SETTING AT BOOT

CONFIGURATION PINS

CLKDIV1 DOMAIN

PLLMS[2:0]

PLL MODE

DEVICE FREQUENCY (SYSCLK1)

(SYSCLK1 DIVIDER)

000

x20

CLKIN x20 / 2

001

x15

CLKIN x15 / 2

010

x16

CLKIN x16 / 2

011

x18

CLKIN x18 / 2

100

x22

CLKIN x22 / 2

101

x25

CLKIN x25 / 2

110

x27

CLKIN x27 / 2

111

x30

CLKIN x30 / 2

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