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数据搜索系统，热门电子元器件搜索 |
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IC-HT 数据表(PDF) 20 Page - IC-Haus GmbH |
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IC-HT 数据表(HTML) 20 Page - IC-Haus GmbH |
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20 / 45 page  prel imin ary prel imin ary iC-HT DUAL CW LASER DIODE DRIVER Rev B1, Page 20/45 Register Address Bits Default Description INITRAM 0x00 0 R/O RAM initialized. PDOVDD 0x00 1 R/O Power down event at VDD MEMERR 0x00 2 R/O RAM memory validation error OVT 0x00 3 R/O Overtemperature event OVC2 0x00 4 R/O Overcurrent at channel 2 OVC1 0x00 5 R/O Overcurrent at channel 1 OSCERR 0x00 6 R/O Oscillator error (watchdog set) CFGTIMO 0x00 7 R/O Configuration mode timeout event MAPC1 0x01 0 R/O Channel 1 current state (on or off) MONC1 0x01 1 R/O Monitor channel 1 enabled at least once (latched) LDKSAT1 0x01 2 R/O Channel 1 LDK saturation event MAPC2 0x01 4 R/O Channel 2 current state (on or off) MONC2 0x01 5 R/O Monitor channel 2 enabled at least once (latched) LDKSAT2 0x01 6 R/O Channel 2 LDK saturation event Table 42: Status registers overview In order to enable the channels, the error events must be acknowledged. Acknowledging an error is accom- plished by reading the STATUS register. After a power- on PDVDD and INITRAM errors will be set, therefore it is required to read STATUS0 and STATUS1 registers after each power-on. Exiting standby mode will not reset the RAM but will set the PDOVDD status bit. Therefore STATUS0 must be read once after each standby to re-enable the laser channels. In case of an overcurrent (OVC) or an overtemperature (OVT) event, laser channels are disabled. A memory error event and a configuration timeout er- ror event will also disable the laser channels. More information about the memory error on page 34. The conditions to enable each laser channel are shown in figure 10. 2 7 5 6 1 4 STATUS0 (Addr. 0x00) 0 PDOVDD MEMERR (Addr. 0x10 ) 1 Pin OVC2 CFGTIMO (Addr. 0x15 ) Pin 3 INITRAM OVT OVC1 1 1 & DISC2 INSOPEN EMCOPEN EC2 MAPC1 DISC1 EC1 MAPC2 & 1 & 1 1 1 & 1 Figure 10: Laser control logic in MCU mode |
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