IC-HT datasheet(21/45 Pages) ICHAUS

21 / 45 page

prel

imin

ary

prel

imin

ary

iC-HT

DUAL CW LASER DIODE DRIVER

Rev B1, Page 21/45

COMBINING BOTH CHANNELS

iC-HT can drive one laser diode up to 1500 mA with

both channels combined.

Therefore register bit MERGE must be set to 1. Dis-

able channel register bits DISC1 and DISC2 must both

be set to 0 and both enable channel pins EC1 and EC2

must be set hi.

MERGE

Addr. 0x1B; bit 6

R/W 0

Channel 1 and 2 operate independently

Power transistor from channel 2 in parallel with

channel 1, controlled by channel 1

Table 43: Channel merging

When both channels are combined the control is done

by channel 1. APC and ACC can both be used with

both channels combined. In ACC mode, the reference

needs be set to 50% of the desired current value. This

is not required for APC.

ACC typical current settings with MERGE = 1

REF1

RACCx=0

RACCx=1

RMERGE=1

MERGE=1

0x000

144.0 mA

18.12 mA

0x001

144.4 mA

18.16 mA

0x010

144.8 mA

18.20 mA

...

0x200

512.4 mA

60.28 mA

0x201

513.6 mA

60.42 mA

0x202

514.8 mA

60.56 mA

...

0x3FD

1692.0 mA

199.54 mA

0x3FE

1696.0 mA

199.54 mA

0x3FF

1700.0 mA

200 mA

Table 44: ACC typical current settings with

MERGE = 1

REF2(7:0)

PLR1

10 Bit

ADCC1(2:0)

DUAL CW LASER DIODE DRIVER

0x14

CFGTIMO

WATCHDOG

TIMER

OSCILLATOR

LASER

CONTROL

0x13

REF1(9:8)

RMD1(7:0)

REGISTERS

SPI/I2C

TEMP(7:0)

0x11

ILIM1(7:0)

0x05

ADC2(9:8)

0x06

ADC2(7:0)

RAM

LASER CHANNEL 1

8 Bit

OVC

MEMERR

0x19

RMD2(7:0)

INTEGRITY

OVT

0x04

ADC1(7:0)

0x10

0x1F

0x30

0x3F

0x16

LASER CHANNEL 2

VDD REGULATOR

TEMPERATURE

0x02

1μF

255

RM1

0x03

ADC1(9:8)

..10 nF..

0x10

10 Bit

APC

8 Bit

ACC

IO DRIVERS

SLAVE

RAM

REF1(7:0)

0x12

1μF

ILIM2(7:0)

CHECK

VB UNDERVOLTAGE

VDD UNDERVOLTAGE

PODO

MONITOR 8 Bit

0x18

REF2(9:8)

0x17

I LDK

CI1

CVB

CVDD

GND

VDD

REF

ADSNF1

EACC1

OVC1

DISP1

EMC

MDA1

AGND2

LDK2

LDK1

CIL1

AGND1

CI2

MDA2

CIL2

MRL2

MRL1

CI1

ECIE1

DCO

GND

Check

NCHK

EC1

NSTBY

INS/WKR

MISO/SDA

SCLK/SCL

MOSI/A0

NCS/A1

EC2

VDD

LDK1

EMC

T.PAD

I LDK

CVB

CVDD

CI1

Figure 11: Combining both channels

In combined mode, the internal CI nodes of both chan-

nels are connected together. If required, an external

capacitor on channel 1 can be used for improved sta-

bility. It is possible to have an additional external ca-

pacitor on channel 2 if ECIE2 bit is set to 1. Having an

external capacitor on channel 2 and none on channel

1 is invalid.

On combined operation both overcurrent thresholds

are active. The overcurrent threshold channel 1 needs

to be set to to 50% and the overcurrent threshold chan-

IC-HT 数据表(PDF) 21 Page - IC-Haus GmbH

IC-HT 数据表(HTML) 21 Page - IC-Haus GmbH

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

数据表下载