 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
IC-HT 数据表(PDF) 41 Page - IC-Haus GmbH |
|
|
|||||||||||||||||||||||||||||
IC-HT 数据表(HTML) 41 Page - IC-Haus GmbH |
|
|
41 / 45 page  prel imin ary prel imin ary iC-HT DUAL CW LASER DIODE DRIVER Rev B1, Page 41/45 Channel 1 configuration registers EACC1 Addr. 0x10; bit 0 R/W 0 0 APC mode enabled for channel 1 (light power regulation) 1 ACC mode enabled for channel 1 (laser current regulation) Table 92: Enable APC/ACC channel 1 ECIE1 Addr. 0x10; bit 1 R/W 0 0 External CI capacitor for channel 1 disconnected 1 External CI capacitor for channel 1 connected Table 93: Enable external CI capacitor channel 1 DISP1 Addr. 0x10; bit 2 R/W 0 0 PLR enabled for channel 1 1 PLR disabled for channel 1 Table 94: Disable PLR channel 1 DISC1 Addr. 0x10; bit 3 R/W 1 0 Channel 1 can be enabled by EC1 pin 1 Channel 1 cannot be enabled by EC1 pin Table 95: Disable channel 1 EOC1 Addr. 0x10; bit 4 R/W 1 0 Channel 1 regulator offset compensation disabled 1 Channel 1 regulator offset compensation enabled Table 96: Enable offset compensation channel 1 ADCC1(2:0) Addr. 0x10; bit 7:5 R/W 000 0xx Channel 1 ADC disabled 100 Channel 1 ADC sourced by V(MDA1), ADSNF1 = 0 100 Channel 1 ADC sourced by V(PLR1), ADSNF1 = 1 101 Channel 1 ADC sourced by V(VB) 110 Channel 1 ADC sourced by V(VDD) 111 Channel 1 ADC sourced by V(LDK1) Table 97: ADC source selection channel 1 ILIM1 Addr. 0x11; bit 7:0 R/W 0xFF 0x0A Channel 1 overcurrent threshold set to the minimum current . . . Channel 1 overcurrent threshold set to Ilim = (∆ I(LDK ) · n), n from 10 to 255 0xFF Channel 1 overcurrent threshold set to the maximum current Table 98: Overcurrent threshold configuration chan- nel 1 RMD1 Addr. 0x12; bit 7:0 R/W 0xFF 0x00 PLR1 set to the minimum resistance . . . PLR1 resistor set to Rmd = Rmd0(1 + ∆ Rmd (%) 100 )n+1, n from 0 to 255 0xFF PLR1 resistor set to the maximum resistance Table 99: MDA resistor channel 1 COMP1 Addr. 0x13; bit 6:4 R/W 011 000 Minimum regulator delay compensation for channel 1, slower response . . . 111 Maximum regulator delay compensation for channel 1, faster response Table 100: Regulator delay compensation channel 1 RLDKS1 Addr. 0x13; bit 3:2 R/W 00 00 V(LDK1) < 0.5 V sets the LDKSAT1 alarm bit 01 V(LDK1) < 0.8 V sets the LDKSAT1 alarm bit 10 V(LDK1) < 1.0 V sets the LDKSAT1 alarm bit 11 V(LDK1) < 1.2 V sets the LDKSAT1 alarm bit Table 101: LDK saturation threshold selection chan- nel 1 REF1 Addr. 0x13/14; bit 9:0 R/W 0x000 0x000 Channel 1 regulator reference voltage set to minimum voltage . . . Channel 1 regulator reference voltage set to Vref = Vref0(1 + ∆ Vref (%) 100 )n+1, n from 0 to 1023 0x3FF Channel 1 regulator reference voltage set to maximum voltage Table 102: Regulator voltage reference channel 1 RACC1 Addr. 0x1A; bit 0 R/W 0 0 Current range high for channel 1 1 Current range low for channel 1 Table 103: Current range configuration channel 1 ADSNF1 Addr. 0x1A; bit 2 R/W 0 0 ADC measurement MDA1 pad (force) 1 ADC measurement PLR1 (sense) Table 104: ADC channel 1 sense/force selection |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
