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STA304A

to a read request the actual value of this signal is returned, not the RAM content. Due to this fact the relative

RAM register content can be incongruous.

•

These three registers are used to setup the sample rate when the Variable Rate Mode is enabled. In re-

sponse to a read request on one of these registers the actual value returned can be either BB80h or AC44h,

depending on the status of an internal hardware signal; the status of this signal is updated every time a write

operation into one of these register is performed.

For more details regarding a specific bit please refer to the appropriate paragraph.

In order to be as much compliant to the specification as possible two different mode of operation has been in-

troduced. Using the

(default): in this mode the value returned as response to a read operation will be properly masked in order to

set ‘reserved’ bits to 0, as from specification. This operation is performed on all registers included the Standard

or Extended Audio address space. If the Full-Compliant mode is not selected the full 16 bits data from the cor-

responding RAM register will be returned with no further manipulation.

If an odd-addressed register reading operation is performed the following scheme is adopted:

•

Slot 0:

report valid bit set to 1 for both slot 1 and slot 2

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Slot 1 (address): report the odd address

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Slot 2 (data):

report all 0s

2.2 Writing AC `97 Registers

When a write operation into one of the available AC`97 registers is performed the entire 16 bits data word is

written into the related RAM register (also

have a corresponding

the value of the FF is also updated every time a write to the related RAM register is performed. The status of

these FF is reverted to their default values after a hardware reset or a software reset (writing to reg. 00h) request

has been issued; as a consequence also the DSP will have to reset the RAM register contents.

Some register may have a different behaviour from the one depicted above. Here is a brief summary of those

registers.

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Regs. 7Ch and 7Eh:

These are the Vendor ID1 and ID2 registers. Any write request to one of these will be ignored.

•

Regs. 28h:

The ‘

•

Regs. 26h:

When a write request is issued the actual data written into the RAM register is ‘xxxxxxxxxxxx1110’, where

‘x’ stands for the incoming data.

•

Regs. 2Ah:

When a write request is issued the actual data written into the RAM register is ‘xxxxxx0111xxxxxx’, where

‘x’ stands for the incoming data.

•

Regs. 32h and 34h:

Any write request into one of these

corresponding RAM register.