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STA304A

4.0 I2S OUTPUT INTERFACE CONFIGURATION

In order to configure the I2S output interface the

I2SO_Align_x bits one of 6 configuration mode can be selected. Following is a table describing each one of

them.

By default standard I2S output interface master is provided (mode 1 in bits 8,9,10 of register CRB,

I2SO_BICK_Pol = 1 and I2SO_LRCK_Pol = 0 in the same register)

4.1 Switching characteristics (10 pf load; Fsm=48 KHz):

Figure 3.

MODE

# of SLOTS

W. LENGHT

ALIGNMENT

DELAY SLOT

NOTES

0

32

24

Left

No

1

32

24

Left

Yes

2

32

16

Right

No

MSb first only

3

32

24

Right

No

4

24

24

Left

No

Slave only

5

Not valid

Not valid

Not valid

Not valid

Reserved, do not use.

6

24

16

Right

No

MSb first only. Slave only

7

24

24

Right

No

Slave only

SCKO frequency (master mode):

64 Fsm

(slave mode):

64 Fsm

min 40 ns.

min 40 ns.

min 20 ns.

min 20 ns.

min 20 ns.

min 20 ns.

min 2 ns; max 8 ns.

min 2 ns; max 8 ns.

(slave mode):

min 6 ns; max 17 ns

D00AU1245

LRCKO

BICKO

SDO