8169 datasheet(8/30 Pages) STMICROELECTRONICS

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STA304A

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3.0 I2S INPUT INTERFACE CONFIGURATION

In order to configure the I2S input interface the

Configuration Register B (CRB) can be used. Using the 3

I2SI_Align_x bits one of 6 configuration mode can be selected. Following is a table describing each one of them.

By default standard I2S input interface slave is provided (mode 1 in bits 0,1,2 of register CRB, I2S_BICK_Pol = 1 and

I2SI_LRCK_Pol = 0 with some register)

3.1 Switching characteristics (10 pf load; Fsm=32 KHz to 96KHz):

Figure 2.

MODE

# of SLOTS

W. LENGHT

ALIGNMENT

DELAY SLOT

NOTES

Left

Yes

Right

MSb first only

Right

Left

Slave only

Not valid

Reserved, do not use.

Right

MSb first only. Slave only

Right

Slave only

BICKI frequency (master mode):

(slave mode):

3.072MHz

Max 6.4 MHz

BICKI pulse width low (T0) (slave mode):

min 40 ns.

BICKI pulse width high (T1) (slave mode):

min 40 ns.

BICKI active to LRCKI edge delay (T2):

min 20 ns.

BICKI active to LRCKI edge setup (T3):

min 20 ns.

SDI valid to BICKI active setup (T4):

min 20 ns.

BICKI active to SDI hold time (T5):

min 20 ns.

BICKI falling to LRCKI edge (T6) (master mode): min 3 ns; max 9 ns.

D00AU1244

LRCKI

BICKI

SDI

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