STA304A

2/30

1.0 DESCRIPTION (continued)

The device supports two main configurations as far as input sources: AC'97 input or IIS/SPDIF input: selection

is made via a dedicated pin (

'Full Compliant' mode and 'Proprietary' mode which enables more features. The selection of the operating mode

is done via a specific bit in a Vendor Reserved register (see bit 0: AC97_FC_mode in the CRA register, address

5Ah).

The 'Full Compliant' mode is compliant with rev. 2.1 of AC`97 link specifications.

This link can provide up to 6 input audio channels with sampling frequency of 44.1, 48, 88.2, 96 kHz, and the

related controls.

In the IIS/SPDIF mode, a stereo S/PDIF and a 4 channels three-wires programmable serial input interface work

in mutually exclusive way. Two channels with sampling frequency in the continuous range from 32 to 96 kHz

are supported by the S/PDIF interface. Up to four channels with sampling frequency varying continuously from

32kHz up to 96 kHz are supported by the programmable serial interfaces. Among the different configurations,

also the standard IIS protocol is supported.

An embedded high quality sample rate converter (SRC) resamples input data at the internal fixed sampling fre-

quency of 48 kHz for DSP operations.

The DSP is a 20x20 bit core audio processor performing several user controlled parametric algorithms, among

them are dynamic and static equalization, Bass, Treble, Volume control and more. The DSP operates at

49.152MHz (1024xfs). This frequency is generated by an internal PLL with programmable multiplication factor

(x2 or x8).

This device has 5 channels Direct Digital Amplification (DDX™ technology), performing high efficiency class-D

PWM output signals used to drive directly external power bridge stages (STA500).

In addition a 6 channel digital output programmable interface (supporting IIS standard protocol) is embedded

for applications with commercial audio D/A converters. The output sampling frequency is fixed at 48 kHz when

the interface operates as master. In addition an oversampled clock (256xfs or 512xfs) is provided externally for

the D/A converters.

An IIC interface allows full programmability of internal algorithms and control registers via an external controller.

An arbitration logic handles access conflicts to embedded control registers (which may occur as a consequence

of contemporary access to control registers by AClink, IIC and DSP blocks).

Figure 1. DSP data processing

BASS

REDIR

STATIC &

DINAMIC

EQ

VOLUME

CENTER

VOLUME

PHANTOM

CENTER

BASS

TREBLE

I2S

SL/SR/LFE

CNT

CNT

L/R

L/R

L/R

L,R,SL,SR,LFE,CNT

L,R,SL,SR,LFE

I2S +

DDX

D01AU1310