STA304A

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DC ELECTRICAL CHARACTERISTICS

2.0 AC’97 BANK REGISTER OVERVIEW

The AC `97 interface is compliant to ‘Audio Codec `97 – Revision 2.1’ specification, as far as the protocol used.

All the registers described in this specification, including Standard, Vendor Reserved and Extended Audio (AC

`97 2.0) registers, are available in this device, but just relevant registers which are described in paragraph 11

(Register Summary) are implemented.

The ATE mode feature has been implemented for test purpose: for related details refer to the

‘Audio Codec `97

2.1 Reading AC `97 Registers

Since the AC`97 register bank has been implemented as a contiguous RAM space (from a DSP point of view)

the content of the RAM itself will be returned as the result of a read operation. This should be followed as a

general rule of thumb but, where not possible, a different approach has been used. Hereby is a list of the reg-

isters, and bits, that do not follow this rule or that have a particular handling:

•

These two bit are respectively bits 14 and 15 of registers 28h (Extended Audio ID) and 3Ch (EWxtended

Modem ID). When a read operation of these registers is performed the returned value is based on the status

of the SA pin: CodecID_0 report the status of SA pin, CodecID_1 always report 0. Other bits of these regis-

ters return the related RAM register contents. Also note that the status of the SA pin is not readable by the

DSP.

The bit 12 of register 26h (Powerdown, ctrl/start) is used to set the AC`97 BIT_CLK and SDATA_IN signal

to a low state. In response to a Warmers the status of this bit is set back to its default 0 value. In response

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

Note

Low Level Input Voltage

V

High Level Input Voltage

V

Low Level Output Voltage

Iol = X mA

V

1,2

High Level Output Voltage

V

1,2

Note 1: Takes into account 200mV voltage drop in both supply lines

Note 2: X is the source/sinc current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability.

Pull-up current

-25

-66

-125

µA1

Equivalent Pull-up resistance

50

K

Ω

Reset Active Time

ns

Master Clock Period

ns

DIGITAL CHARACTERISTICS-SPDIF RECEIVER (RXP,RXN pins only, SPDIF - MODE = ANALOG)

ZIN

Input Resistance

k

Ω

VTH

Dufferential Input Voltage

200

mV

VHY

Input Hysteresis

50

mV

1

49.152

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