8169 datasheet(23/30 Pages) STMICROELECTRONICS

23 / 30 page

23/30

STA304A

12.9 Configuration Register A (CRA) : add. 5Ah

NOTE: In TEST_MODE -> PLL_Bypass = 0.

Table 1. SRC Threshold

D15

D14

D13

D12

D11

D10

SRC_By

pass

DRLL_d

SRC_TH

R_1

SRC_TH

R_0

SPDIF_

Mode

I2S_SP

DIF_Sel

MCKOU

T_Mode

PLL_By

pass

PLL_Fac

tor

DDX_P

wrMode

DDX_ZD

_Enable

DDX_Rst DDX_Ga

in_1

DDX_Ga

in_0

I2SI_DBU

FF_Mode

AC97_F

C_Mode

BIT

R/W

RST

NAME

DESCRIPTION

R/W

AC97_FC_Mode

AC’97 Full Compliant Mode (0 to enable). When in FC mode any read

of registers will return only valid bits: bits marked as ‘reserved’ by

AC’97 v2.0 specification will return 0, regardless of the RAM

contents.

R/W

I2SI_DBUFF_Mode

Enable DoubleBuffer mode for the I2S input interface (write1 to

enable this option) . This is strongly required if this interface is

operated in slave mode at 48KHz, synchronous with the input source.

In this condition also Sample Rate Converter Bypass is suggested to

omprove performances

R/W

DDX_Gain_0

DDX Gain setting (LSb/MSb). These two bits, concatenated, will set

the DDX stage gain and the compression as shown in Table 1.

(These setting is active only if bit 15 reg 62h is 0)

R/W

DDX_Gain_1

R/W

DDX_Rst

DDX Reset (active high)

R/W

DDX_ZD_Enable

DDX Zero Detect feature. If this bit is 1 the feature is enabled.

R/W

DDX_PwrMode

DDX Power Mode (TRUTH Table). Using this bit it is possible to select

the truth table used by the DDX digital output stage (1 = ST standard)

R/W

PLL_Factor

PLL Factor (x2 or x8). It should be used according to the input

frequency provided to the device: 1 (x8) when 6.144 MHz are

provided, 0 (x2) when 24.576 MHz.

R/W

PLL_Bypass

PLL Bypass. Setting this bit to 0 will bypass the PLL; internal master

clock will be directly connected to XTI pin.

R/W

MCKOUT_Mode

MckOut mode: 12.288 MHz (1) or 24.576 MHz (0).

R/W

I2S_SPDIF_Sel

I2S - S/PDIF Selector. Select the input source: set to 0 for I2S input, 1

for S/PDIF input.

R/W

SPDIF_Mode

S/PDIF Mode. Set to 0 to select Analog mode, 1 to select Digital

mode.

R/W

SRC_THR_0

Sample Rate threshold (LSb/MSb). These bits are used to select the

threshold frequency enabling the SRC anti-alias filter.

R/W

SRC_THR_1

Table 2 shows the threshold selections.

R/W

DRLL_dbg

DRLL Debug Mode. When this mode is activated (1) the DRLL digital

ratio is latched on the output channels instead of the audio data.

R/W

SRC_Bypass

SRC Bypass. Setting this bit to 1 the SRC block can be bypassed and

the selected input I/F is directly connected to the DSP.

SRC_THR_0

SRC_THR_1

Threshold Frequency

INACTIVE

58.875 to 61.125kHz

78.973 to 81.000kHz

always active

8169 数据表(PDF) 23 Page - STMicroelectronics

8169 数据表(HTML) 23 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

数据表下载