80960JD datasheet(29/59 Pages) INTEL

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80960JD

PRODUCT PREVIEW

4.4

VCC5 Pin Requirements (VDIFF)

In mixed voltage systems where the processor is

components, VCC5 must be connected to 5 volts.

This allows proper 5 volt tolerant buffer operation,

and prevents damage to the input pins. The voltage

differential between the 80960Jx VCC5 pin and its 3.3

volt VCC pins must not exceed 2.25 volts. If this

requirement is not met, current flow through the pin

may exceed the value at which the processor is

damaged. Instances when the voltage can exceed

2.25 volts is during power up or power down, where

one source reaches its level faster than the other,

briefly

causing

excess

voltage

differential.

Another instance is during steady-state operation,

where the differential voltage of the regulator

(provided a regulator is used) cannot be maintained

within 2.25 volts. Two methods are possible to

prevent this from happening:

• Use a regulator that is designed to prevent the

voltage differential from exceeding 2.25 volts, or,

As shown in Figure 6, place a 100

Ω resistor in series

with the VCC5 pin to limit the current through VCC5.

Figure 6. VCC5 Current-Limiting Resistor

• If the regulator cannot prevent the 2.25 volt differ-

ential, the addition of the resistor is a simple and

reliable method for limiting current. The resistor

can also prevent damage in the case of a power

failure, where the 5 volt supply remains on and the

3.3 volt supply goes to zero.

In 3.3 volt only systems where the 80960Jx input

pins are driven from 3.3 volt logic, connect the VCC5

pin directly to the 3.3 volt VCC plane.

+5 V (±0.25 V)

VCC5 Pin

100

Ω

(±5%, 0.5 W)

Symbol

Parameter

Min

Max

Units

Notes

VDIFF

VCC5-VCC

Difference

2.25

VCC5 input should not exceed VCC by more than 2.25 V

during power-up and power-down, or during steady-state

operation.

4.5

VCCPLL Pin Requirements

To reduce clock jitter on the i960 Jx processor, the

VCCPLL pin for the Phase Lock Loop (PLL) circuit is

isolated on the pinout. The lowpass filter, as shown

in Figure 7, reduces noise induced clock jitter and its

effects on timing relationships in system designs.

The 4.7 µF capacitor must be (low ESR solid

tantalum), the 0.01 µF capacitor must be of the type

X7R and the node connecting VCCPLL must be as

short as possible.

Figure 7. VCCPLL Lowpass Filter

100

VCC

(Board Plane)

VCCPLL

(On i960 Jx processors)

Ω (±5%, 1/8 W)

F_CA078A

0.01µF

4.7µF

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