80960JD datasheet(4/59 Pages) INTEL

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Contents

FIGURES

Figure 1.

80960JD Microprocessor ................................................................................................................ i

Figure 2.

80960JD Block Diagram ................................................................................................................ 2

Figure 3.

132-Lead Pin Grid Array Bottom View - Pins Facing Up ............................................................. 12

Figure 4.

132-Lead Pin Grid Array Top View - Pins Facing Down .............................................................. 13

Figure 5.

132-Lead PQFP - Top View ......................................................................................................... 16

Figure 6.

VCC5 Current-Limiting Resistor ................................................................................................... 23

Figure 7.

VCCPLL Lowpass Filter ............................................................................................................... 23

Figure 8.

AC Test Load ............................................................................................................................... 29

Figure 9.

Output Delay or Hold vs. Load Capacitance ................................................................................ 29

Figure 10.

CLKIN Waveform ......................................................................................................................... 30

Figure 11.

Output Delay Waveform for TOV1 ................................................................................................30

Figure 12.

Output Float Waveform for TOF ...................................................................................................31

Figure 13.

Input Setup and Hold Waveform for TIS1 and TIH1 ......................................................................31

Figure 14.

Input Setup and Hold Waveform for TIS2 and TIH2 ......................................................................32

Figure 15.

Input Setup and Hold Waveform for TIS3 and TIH3 ......................................................................32

Figure 16.

Input Setup and Hold Waveform for TIS4 and TIH4 ......................................................................33

Figure 17.

Relative Timings Waveform for TLX, TLXL and TLXA ....................................................................33

Figure 18.

DT/R and DEN Timings Waveform .............................................................................................. 34

Figure 19.

TCK Waveform ............................................................................................................................ 34

Figure 20.

Input Setup and Hold Waveforms for TBSIS1 and TBSIH1 .............................................................35

Figure 21.

Output Delay and Output Float Waveform for TBSOV1 AND TBSOF1 ............................................35

Figure 22.

Output Delay and Output Float Waveform for TBSOV2 and TBSOF2 .............................................36

Figure 23.

Input Setup and Hold Waveform for TBSIS2 and TBSIH2 ...............................................................36

Figure 24.

Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus .................................. 37

Figure 25.

Burst Read and Write Transactions Without Wait States, 32-Bit Bus .......................................... 38

Figure 26.

Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus ................................................... 39

Figure 27.

Burst Read and Write Transactions Without Wait States, 8-Bit Bus ............................................ 40

Figure 28.

Burst Read and Write Transactions With 1, 0 Wait States

and Extra Tr State on Read, 16-Bit Bus ....................................................................................... 41

Figure 29.

Bus Transactions Generated by Double Word Read Bus Request,

Misaligned One Byte From Quad Word Boundary, 32-Bit Bus, Little Endian .............................. 42

Figure 30.

HOLD/HOLDA Waveform For Bus Arbitration ............................................................................. 43

Figure 31.

Cold Reset Waveform .................................................................................................................. 44

Figure 32.

Warm Reset Waveform ................................................................................................................ 45

Figure 33.

Entering the ONCE State ............................................................................................................. 46

Figure 34.

Summary of Aligned and Unaligned Accesses (32-Bit Bus) ........................................................ 49

Figure 35.

Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued) .................................... 50

Figure 36.

80960JD Device Identification Register ....................................................................................... 51

80960JD 数据表(PDF) 4 Page - Intel Corporation

80960JD 数据表(HTML) 4 Page - Intel Corporation

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