80960JD datasheet(34/59 Pages) INTEL

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80960JD

PRODUCT PREVIEW

Table 17. Note Definitions for Table 16, 80960JD AC Characteristics (pg. 26)

NOTES:

1. Not tested.

2. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter

frequency spectrum should not have any power peaking between 500 KHz and 1/3 of the CLKIN

frequency.

3. Inactive ALE/ALE refers to the falling edge of ALE and the rising edge of ALE. For inactive ALE/ALE

timings, refer to Relative Output Timings in this table.

4. A float condition occurs when the output current becomes less than ILO. Float delay is not tested, but is

designed to be no longer than the valid delay.

5. AD31:0 are synchronous inputs. Setup and hold times must be met for proper processor operation. NMI

and XINT7:0 may be synchronous or asynchronous. Meeting setup and hold time guarantees recog-

nition at a particular clock edge. For asynchronous operation, NMI and XINT7:0 must be asserted for a

minimum of two CLKIN periods to guarantee recognition.

6. RDYRCV and HOLD are synchronous inputs. Setup and hold times must be met for proper processor

operation.

7. RESET may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a

particular clock edge.

8. ONCE and STEST must be stable at the rising edge of RESET for proper operation.

9. Guaranteed by design. May not be 100% tested.

10. Relative to falling edge of TCK.

11. Worst-case TOV condition occurs on I/O pins when pins transition from a floating high input to driving a

low output state. The Address/Data Bus pins encounter this condition between the last access of a read,

and the address cycle of a following write. 5 V signals take 3 ns longer to discharge than 3.3 V signals at

50 pF loads.

80960JD 数据表(PDF) 34 Page - Intel Corporation