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LTC1609ACSW 数据表(PDF) 8 Page - Linear Technology |
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LTC1609ACSW 数据表(HTML) 8 Page - Linear Technology |
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8 / 24 page ![]() 8 LTC1609 1609fa 16-BIT CAPACITIVE DAC COMP REF BUF 2.5V REF CAP (2.5V) CSAMPLE CSAMPLE DATA DATACLK SYNC BUSY CONTROL LOGIC R/C PWRD SB/BTC EXT/INT TAG INTERNAL CLOCK CS ZEROING SWITCHES VDIG VANA R1IN R2IN R3IN REF AGND1 AGND2 DGND 1609 BD + – SUCCESSIVE APPROXIMATION REGISTER SERIAL INTERFACE 4k 20k 10k 5k 20k FUNCTIONAL BLOCK DIAGRA APPLICATIO S I FOR ATIO Conversion Details The LTC1609 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 16-bit serial output. The ADC is complete with a precision reference and an internal clock. The control logic provides easy interface to microprocessors and DSPs. (Please refer to the Digital Interface section for timing information.) Conversion start is controlled by the CS and R/C inputs. At the start of conversion the successive approximation register (SAR) is reset. Once a conversion cycle has begun it cannot be restarted. During the conversion, the internal 16-bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). Referring to Figure 1, VIN is connected through the resistor divider to the sample-and-hold capacitor during the acquire phase and the comparator offset is nulled by the autozero switches. In this acquire phase, a minimum delay of 2 µs will provide enough time for the sample-and-hold capacitor to acquire the analog signal. During the convert phase, the autozero switches open, putting the comparator into the compare mode. The input switch switches CSAMPLE to ground, injecting the analog input charge onto the summing junc- tion. This input charge is successively compared with the binary-weighted charges supplied by the capacitive DAC. Bit decisions are made by the high speed comparator. At VDAC 1609 F01 + – CDAC DAC SAMPLE HOLD CSAMPLE S A R 16-BIT SHIFT REGISTER COMPARATOR SAMPLE SI RIN2 RIN1 VIN Figure 1. LTC1609 Simplified Equivalent Circuit |
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