17

LTC1609

1609fa

APPLICATIO S I FOR ATIO

DATA

SYNC

BUSY

R/C

B1

B14

B15

(MSB)

B0

1606 F11

012

15

16

EXTERNAL

DATACLK

To minimize the possible external disturbances that can

occur while a conversion is in progress, the data needs to

be shifted out within 1.2

µs from the start of the conver-

sion. Using the maximum data clock frequency of 20MHz

will ensure this condition is met.

External Data Clock Data Read During the Conversion

Figure 12 shows how the result from the previous conver-

sion can be read out during the current conversion. The

externally supplied data clock is running continuously. CS

and R/C are used to initiate a conversion and read the data

from the previous conversion. The conversion starts on

the falling edge of CS after R/C is low. A pulse on the SYNC

pin will be generated on the first rising edge of DATACLK

#1 after R/C has returned high. The SYNC output can be

captured on the falling edge of DATACLK #1 or on the

rising edge of DATACLK #2. After the rising edge of

DATACLK #2 the SYNC output will go low and the MSB will

be clocked out on the DATA pin. This bit can be latched on

the falling edge of DATACLK #2 or on the rising edge of

DATACLK #3. The LSB will be valid on the falling edge of

DATACLK #17 or the rising edge of DATACLK #18. After

the rising edge of DATACLK #18 the DATA pin will take on

the value of the TAG pin that occurred at the rising edge of

DATACLK #2.

To minimize the possible external disturbances that can

occur while a conversion is in progress, the data needs to

be shifted out within 1.2

µs from the start of the conver-

sion. Using the maximum data clock frequency of 20MHz

will ensure this condition is met. Since there is no through-

put penalty for clocking the data out after the conversion,

clocking the data out during the conversion is not recom-

mended.

Use of the TAG Input

The TAG input pin is used to daisy-chain multiple convert-

ers. This is useful for applications where hardware con-

straints may limit the number of lines needed to interface

to a large number of converters. This mode of operation

works only using the external clock method of shifting out

the data.

Figure 13 shows how this feature can be used. R/C, CS and

the DATACLK are tied together on both LTC1609s. CS can

be grounded if a discontinuous data clock is used. A falling

edge on R/C will allow both LTC1609s to capture their

respective analog input signals simultaneously. Once the

conversion has been completed the external data clock

DCLK is started. The MSB from device #1 will be valid after

the rising edge of DCLK #1. Once the LSB from device #1

has been shifted out on the rising edge of DCLK #16, a null

Figure 11. Conversion and Read Timing Using a Discontinuous Data Clock (EXT/INT Tied High, CS Tied Low).

Read Previous Conversion Result During the Conversion. For Best Performance, Complete Read in Less Than 1.2

µs