14

LTC1609

1609fa

Power Shutdown

When the PWRD pin is tied high, power consumption

drops to a typical value of 50

µW from a specified maxi-

mum of 100mW. In the power shutdown mode, the result

from the previous conversion is still available in the

internal shift register, assuming the data had not been

clocked out before going into power shutdown.

The internal reference buffer and the reference are shut

down, so the power-up recovery time will be dependent

upon how fast the bypass capacitors on these pins can be

charged. If the internal reference is used, the 4k resistor in

series with the output and the external bypass capacitor,

typically 2.2

µF, will be the main time constant for the

power-up recovery time. If an external reference is used,

the reference buffer output will be able to ramp from 0V to

2.5V in 1ms, while charging a typical bypass capacitor of

2.2

µF. The recovery time will be less if the bypass capaci-

tor has not completely discharged.

DIGITAL INTERFACE

Internal Conversion Clock

The ADC has an internal clock that is trimmed to achieve

a typical conversion time of 2.7

µs. No external adjust-

ments are required and, with the typical acquisition time of

1.5

µs, throughput performance of 200ksps is assured.

Timing and Control

Conversion start and data read are controlled by two

digital inputs: CS and R/C. To start a conversion and put

the sample-and-hold into the hold mode bring CS and

R/C low for no less than 40ns. Once initiated it cannot be

restarted until the conversion is complete. Converter

status is indicated by the BUSY output and this is low while

the conversion is in progress.

The conversion result is clocked out serially on the DATA

pin. It can be synchronized by using the internal data clock

or by using an external clock provided by the user. Tying

the EXT/INT pin high puts the LTC1609 in the external

clock mode and the DATACLK pin is a digital input. Tying

the EXT/INT pin low puts the part in the internal clock mode

and the DATACLK pin becomes a digital output.

Internal Clock Mode

With the EXT/INT pin tied low, the LTC1609 provides the

data clock on the DATACLK pin. The timing diagram is

shown in Figure 8. Typically, CS is tied low and the R/C

pin is used to start a conversion. During the conversion

a 16-bit word will be shifted out MSB-first on the DATA

pin. This word represents the result from the previous

conversion. The DATACLK pin outputs 16 clock pulses

used to synchronize the data. The output data is valid on

both the rising and falling edges of the clock. After the

LSB bit has been clocked out, the DATA pin will take on

the state of the TAG pin at the start of the conversion. The

DATACLK pin goes low until the next conversion is

requested. The data clock is derived from the internal

conversion clock. To avoid errors from occurring during

the current conversion, minimize the loading on the

DATACLK pin and the DATA pin. For the best conversion

results the external clock mode is recommended.

APPLICATIO S I FOR ATIO

Figure 8. Serial Data Timing Using Internal Clock (CS, EXT/INT and TAG Tied Low)

B14

B13

B2

B1

B0

1609 F08

B15

(MSB)

BUSY

DATA

DATACLK

R/C

2

3

14

15

16

1