16

LTC1609

1609fa

External Data Clock Data Read After the Conversion

Figure 10 shows how the result from the current conver-

sion can be read out after the conversion has been com-

pleted. The externally supplied data clock is running

continuously. CS and R/C are first used together to initiate

a conversion and then CS is used to read the result. The

conversion starts on the falling edge of CS with R/C low.

Both CS and R/C should be returned high within 1.2

µs to

prevent the transition from disturbing the conversion.

After the conversion has been completed (BUSY returning

high), a pulse on the SYNC pin will be generated after the

first rising edge of DATACLK #1 that occurs after CS goes

low (R/C high). The SYNC output can be captured on the

falling edge of DATACLK #1 or on the rising edge of

DATACLK #2. After the rising edge of DATACLK #2, the

SYNC output will go low and the MSB will be clocked out

on the DATA pin. This bit can be latched on the falling edge

of DATACLK #2 or on the rising edge of DATACLK #3. The

LSB will be valid on the falling edge of DATACLK #17 or the

rising edge of DATACLK #18. After the rising edge of

DATACLK #18 the DATA pin will take on the value of the

TAG pin that occurred at the rising edge of DATACLK #2.

Using the highest frequency permitted for DATACLK

(20MHz), shifting the data out after the conversion will not

degrade the 200kHz throughput.

External Discontinuous Data Clock Data Read

During the Conversion

Figure 11 shows how the result from the previous conver-

sion can be read out during the current conversion. The

externally supplied data clock is running discontinuously.

R/C is used to initiate a conversion with CS tied low. The

conversion starts on the falling edge of R/C. R/C should be

returned high within 1.2

µs to prevent the transition from

disturbing the conversion. A pulse on the SYNC pin will be

generated on rising edge of DATACLK #0. The SYNC

output can be captured on the falling edge of DATACLK #0

or on the rising edge of DATACLK #1. After the rising edge

of DATACLK #1, the SYNC output will go low and the MSB

will be clocked out on the DATA pin. This bit can be latched

on the falling edge of DATACLK #1 or on the rising edge of

DATACLK #2. The LSB will be valid on the falling edge of

DATACLK #16. Another clock pulse would be needed if the

LSB is captured on a rising edge. A minimum of 17 clock

pulses are required if the data is captured on falling clock

edges.

APPLICATIO S I FOR ATIO

0

1

2

3

4

17

18

TAG0

TAG

DATA

SYNC

BUSY

R/C

CS

EXTERNAL

DATACLK

TAG1

TAG2

TAG15

B1

B14

B15

(MSB)

B0

TAG0

TAG1

TAG16

TAG17

TAG18

TAG19

1606 F10

Figure 10. Conversion and Read Timing with External Clock (EXT/INT Tied High). Read After Conversion