18

LTC1609

1609fa

TAG0

TAG

DATA

SYNC

BUSY

R/C

CS

TAG1

TAG2

TAG3

TAG15

B1

B14

B13

B15

(MSB)

B0

TAG0

TAG1

TAG16

TAG17

TAG18

TAG19

1606 F12

0

1

2

3

4

16

17

18

EXTERNAL

DATACLK

Figure 12. Conversion and Read Timing Using an External Data Clock (EXT/INT Tied High).

Read Previous Conversion Result During the Conversion. For Best Performance, Complete Read in Less Than 1.2

µs

APPLICATIO S I FOR ATIO

DATA

CS

R/C

DCLK

DCLK IN

R/C IN

CS IN

TAG

LTC1609

#2

DATA

CS

R/C

DCLK

TAG

DATA OUT

1609 F13

LTC1609

#1

Figure 13. Two LTC1609s Cascaded

Together Using the TAG Input

bit will be shifted out on the following clock pulse before

the MSB from device #2 becomes available (Figure 14).

The reason for this is the MSB from device #2 will not be

valid soon enough to meet the minimum setup time of

device #1’s TAG input. A minimum of 34 clock pulses are

needed to shift out the results from both LTC1609s

assuming the data is captured on the falling clock edge.

Using the highest frequency permitted for DATACLK

(20MHz), a 200kHz throughput can still be achieved.