AD9856SLASHPCB datasheet(31/37 Pages) AD

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AD9856

Rev. C | Page 30 of 36

PROGRAMMING/WRITING THE AD8320/AD8321

CABLE DRIVER AMPLIFIER GAIN CONTROL

Programming the gain control register of the AD8320/AD8321

programmable cable driver amplifier can be accomplished via

the AD9856 serial port. Four 8-bit registers (one per profile)

within the AD9856 store the gain value to be written to the

AD8320/AD8321. The AD8320/AD8321 is written via three

dedicated AD9856 output pins that are directly connected

to the AD8320/AD8321 serial input port. The transfer of

data from the AD9856 to the AD8320/AD8321 requires

136 SYSCLK clock cycles and occurs upon detection of three

conditions. Each condition is described next.

Power-Up Reset

Upon initial power up, the AD9856 clears (Logic 0) the contents

of control registers 07h, 0Dh, 13h, and 19h, which defines the

lowest gain setting of the AD8320/AD8321. Thus, the AD9856

writes all 0s out of the AD8320/AD8321 serial interface.

Change in Profile Selection Bits (PS1, PS0)

The AD9856 samples the PS1, PS0 input pins and writes to the

AD8320/ AD8321 gain control register when a change in profile

is determined. The data written to the AD8320/AD8321 comes

from the AD9856 gain control register associated with the

current profile.

Serial Port Write of AD9856 Registers Containing

AD8320/AD8321 Data

The AD9856 writes to the AD8320/AD8321 with data from the

gain control register associated with the current profile

whenever any AD9856 gain control register is updated. The

user does not have to write the AD9856 in any particular order

or to be concerned with time between writes. If the AD9856 is

currently writing to the AD8320/AD8321 while one of the four

AD9856 gain control registers is being addressed, the AD9856

immediately terminates the AD8320/AD8321 write sequence

(without updating the AD8320/AD8321) and begins a new

AD8320/AD8321 write sequence.

GAIN TRANSFER

CA ENABLE

CA CLK

tDS

CA DATA

VALID DATA WORD G1

MSB...LSB

VALID DATA WORD G2

tWH

tCK

tES

tEH

8 CLOCK CYCLES

SYMBOL

DEFINITION

MIN

tDS

CA DATA SETUP TIME

6.5ns

tDH

CA DATA HOLD TIME

2ns

tWH

CA CLOCK PULSE HIGH

9ns

tCK

CA CLOCK PERIOD

25ns

tES

CA ENABLE SETUP TIME

17ns

tEH

CA ENABLE HOLD TIME

2.0ns

Figure 50. Programmable Cable Driver Amplifier Output Control Interface Timing

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