AD9856SLASHPCB datasheet(18/37 Pages) AD

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AD9856

Rev. C | Page 17 of 36

For continuous-mode input timing, the TxENABLE pin can

be thought of as a data input clock running at half the input

sample rate (fW/2). In addition to synchronization, for contin-

uous mode timing, the TxENABLE input indicates whether an

I or Q input is being presented to the D<11:0> pins. It is

intended that data is presented in alternating fashion such that

I data is followed by Q data. Stated another way, the TxENABLE

pin should maintain approximately a 50/50 duty cycle. As in

burst mode, the rising edge of TxENABLE synchronizes the

AD9856 to the input data rate and the data is registered at the

approximate center of the data-valid time. The continuous

operating mode can only be used in conjunction with the full-

word input format.

Burst Mode Input Timing

Figure 24 through Figure 28 show the input timing relationship

between TxENABLE and the 12-bit input data-word for all

three input format modes when the AD9856 is configured for

burst input timing. Also shown in these diagrams is the time-

aligned, 12-bit parallel I/Q data as assembled by the AD9856.

Figure 24 shows the classic burst-mode timing, for full-word

input mode, in which TxENABLE frames the input data stream.

Note that sequential input of alternating I/Q data, starting with

I data, is required.

The input sample rate for full-word mode, when the third half-

band filter is engaged, is given by

SYSCLK

fIN

where N is the CIC interpolation rate.

The input sample rate for full-word mode, when the third half-

band filter is not engaged is given by:

SYSCLK

fIN

where N is the CIC interpolation rate

Figure 25 shows an alternate timing method for TxENABLE

when the AD9856 is configured in full-word, burst-mode

operation. The benefit of this timing is that the AD9856

resynchronizes the input sampling logic when the rising edge of

TxENABLE is detected. The low time on TxENABLE is limited

to one input sample period and must be low during the Q data

period. The maximum high time on TxENABLE is unlimited.

Thus, unlimited high time on TxENABLE results in the timing

diagram of Figure 24. See Figure 28 for the ramifications of

violating the TxENABLE low time constraint when operating

in burst mode.

Figure 26 shows the input timing for half-word mode, burst

input timing operation.

In half-word mode, data is input on the D<11:6> inputs. The

D<5:0> inputs are unused in this mode and should be tied to

DGND or DVDD. The AD9856 expects the data to be input

in the following manner: I<11:6>, I<5:0>, Q<11:6>, Q<5:0>.

Data is twos complement; the sign bit is D<11> in the notation

I<11:0>, Q<11:0>.

The input sample rate for half-word mode, when the third half-

band filter is engaged, is given by

SYSCLK

fIN

where N is the CIC interpolation rate.

The input sample rate for half-word mode, when the third half-

band filter is not engaged is given by:

SYSCLK

fIN

where N is the CIC interpolation rate.

Figure 27 shows the input timing for quarter-word, burst input

timing operation.

In quarter-word mode, data is input on the D<11:9> inputs. The

D<8:0> inputs are unused in this mode and should be tied to

DGND or DVDD. The AD9856 expects the data to be input in

the following manner: I<11:9>, I<8:6>, I<5:3>, I<2:0>,

Q<11:9>, Q<8:6>, Q<5:3>, Q<2:0>. Data is twos complement;

the sign bit is D<11> in the notation I<11:0>, Q<11:0>.

The input sample rate for quarter-word mode, when the third

half-band filter is engaged, is given by:

SYSCLK

f IN

where N is the CIC interpolation rate.

Note that Half-Band Filter 3 must be engaged when operating

in quarter-word mode.

Figure 28 describes the end of burst timing and internal data

assembly. Note that in burst-mode operation, if the TxENABLE

input is low for more than one input sample period, numerical

zeros are internally generated and passed to the data path logic

for signal processing. This is not valid for continuous-mode

operation, as is discussed later.

To ensure proper operation, the minimum time between falling

and rising edges of TxENABLE is one input sample period.

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