AD9856SLASHPCB datasheet(32/37 Pages) AD

32 / 37 page

AD9856

Rev. C | Page 31 of 36

UNDERSTANDING AND USING PIN-SELECTABLE

MODULATOR PROFILES

The AD9856 quadrature digital upconverter is capable of

storing four preconfigured modulation modes called profiles

that define the following:

•

Output frequency—32 bits

•

Interpolation rate—6 bits

•

Spectral inversion status—1 bit

•

Bypass third half-band filter—1 bit

•

Gain control of AD8320/AD8321—8 bits

Output Frequency

This attribute consists of four 8-bit words loaded into four

(FTW) for each profile. The lowest register address corresponds

to the least significant 8-bit word. Ascending addresses

correspond to increasingly significant 8-bit words. The output

frequency equation is given as: fOUT = (FTW × SYSCLK)/232.

Interpolation Rate

Consists of a 6-bit word representing the allowed interpolation

values from 2 to 63. Interpolation is the mechanism used to up

sample or multiply the input data rate such that it exactly

matches that of the DDS sample rate (SYSCLK). This implies

that the system clock must be an exact multiple of the symbol

rate. This 6-bit word represents the 6 MSBs of the eight bits

allocated for that address. The remaining two bits contain the

spectral inversion status bit and half-band bypass bit.

Spectral Inversion

Single bit that when at Logic 0 the default or noninverted

output from the adder is sent to the following stages. A Logic 1

causes the inverted output to be sent to the following stages.

The noninverted output is described as

I × Cos(ωt) − Q × Sin(ωt).

The inverted output is described as

I × Cos(ωt) + Q × Sin(ωt).

This bit is located adjacent to the LSB at the same address as the

interpolation rate previously described.

Bypass Third Half-Band Filter

A single bit located in the LSB position of the same address as

the interpolation rate. When this bit is Logic 0, the third half-

band filter is engaged and its inherent 2× interpolation rate is

applied. When this bit is Logic 1, the third half-band filter is

bypassed and the 2× interpolation rate is negated. This allows

users to input higher data rates—rates that may be too high for

the minimum interpolation rate if all three half-band filters

with their inherent 2× interpolation rate are engaged. The effect

is to reduce the minimum interpolation rate from 8× to 4×.

AD8320/AD8321 Gain Control

An 8-bit word that controls the gain of an AD8320/AD8321

programmable gain amplifier connected to the AD9856 with

the 3-bit SPI interface bus. Gain range is from −10 dB (00 hex)

to +26 dB (FFhex). The gain is linear in V/V/LSB and follows

the equation AV = 0.316 + 0.077 × Code, where Code is the

decimal equivalent of the 8-bit gain word.

Profile Selection

After profiles have been loaded into the appropriate registers,

the user may select which profile to use with two input pins:

PS0 and PS1, Pins 45 and 46. Table 9 shows how profiles are

selected.

Table 9. Profile Select Matrix

PS1

PS0

PROFILE

Except while in single-tone mode, it is recommended that users

suspend the TxENABLE function by bringing the pin to Logic 0

prior to changing from one profile to another and then re-

asserting TxENABLE. This assures that any discontinuities

resulting from register data transfer are not transmitted up or

downstream. Furthermore, changing interpolation rates during

a burst may create an unrecoverable digital overflow condition

that interrupts transmission of the current burst until a RESET

and reloading procedure is completed.

POWER DISSIPATION CONSIDERATIONS

The majority of the AD9856 power dissipation comes from

digital switching currents. As such, power dissipation is highly

dependent upon chip configuration.

The major contributor to switching current is the maximum

clock rate at which the device is operated, but other factors can

play a significant role. Factors such as the CIC interpolation

rate, and whether the third half-band filter and inverse SINC

filters are active, can affect the power dissipation of the device.

It is important for the user to consider all of these factors when

optimizing performance for power dissipation. For example,

there are two ways to achieve a 6 MS/s transmission rate with

the AD9856. The first method uses an fMAX of 192 MHz; the

other method uses an fMAX of 144 MHz, which reduces power

dissipation by nearly 25%.

For the first method, the input data must be externally 4×

upsampled. The AD9856 must be configured for a CIC

interpolation rate of three while bypassing the 3rd half-band

filter. This results in an I/Q input sample rate of 24 MHz which

is further upsampled by a factor of 8 MHz to 192 MHz.

AD9856/PCB 数据表(PDF) 32 Page - Analog Devices

AD9856/PCB 数据表(HTML) 32 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

数据表下载