AD9856SLASHPCB datasheet(16/37 Pages) AD

16 / 37 page

AD9856

Rev. C | Page 15 of 36

THEORY OF OPERATION

To gain a general understanding of the functionality of the

AD9856, it is helpful to refer to Figure 23, a block diagram of

the device architecture. The following is a general description of

the device functionality. Later sections detail each of the data

path building blocks.

MODULATION MODE OPERATION

The AD9856 accepts 12-bit data-words, which are strobed into

the data assembler via an internal clock. The input, TxENABLE,

serves as the valve that allows data to be accepted or ignored by

the data assembler. The user has the option to feed the 12-bit

data-words to the AD9856 as single 12-bit words, dual 6-bit

words, or quad 3-bit words. This provides the user with the

flexibility to use fewer interface pins, if desired. Furthermore,

the incoming data is assumed to be complex in that alternating

12-bit words are regarded as the inphase (I) and quadrature (Q)

components of a symbol.

The rate at which the 12-bit words are presented to the AD9856

is referred to as the input sample rate (fIN). Note that fIN is not

the same as the baseband data rate provided by the user. Rather,

the user’s baseband data is required to be upsampled by at least

a factor of two (2) before being applied to the AD9856 in order

to minimize the frequency-dependent attenuation associated

with the CIC filter stage (see the Cascaded Integrator Comb

(CIC) Filter section ).

The data assembler splits the incoming data-word pairs into

separate I/Q data streams. The rate at which the I/Q data-word

pairs appear at the output of the data assembler is referred to as

the I/Q sample rate (fIQ). Because two 12-bit input data-words

are used to construct the individual I and Q data paths, the

input sample rate is twice the I/Q sample rate (i.e., fIN = 2 × fIQ).

Once through the data assembler, the I/Q data streams are fed

through two half-band filters (Half-Band Filters 1 and 2). The

combination of these two filters results in a factor of four (4)

increase of the sample rate. Thus, at the output of Half-Band

Filter 2, the sample rate is 4 × fIQ. In addition to the sample rate

increase, the half-band filters provide the low-pass filtering

characteristic necessary to suppress the spectral images

produced by the upsampling process. Further upsampling is

available via an optional third half-band filter (Half-Band

Filter 3). When selected, this provides an overall upsampling

factor of eight (8). Thus, if Half-Band Filter 3 is selected, the

sample rate at its output is 8 × fIQ.

After passing through the half-band filter stages, the I/Q data

streams are fed to a cascaded integrator comb (CIC) filter.

This filter is configured as an interpolating filter, which allows

further upsampling rates of any integer value between 2 and 63,

inclusive. The CIC filter, like the half-bands, has a built-in low-

pass characteristic. Again, this provides for suppression of the

spectral images produced by the upsampling process.

The digital quadrature modulator stage following the CIC

filters is used to frequency shift the baseband spectrum of

the incoming data stream up to the desired carrier frequency

(a process known as upconversion). The carrier frequency is

controlled numerically by a direct digital synthesizer (DDS).

The DDS uses its internal reference clock (SYSCLK) to generate

the desired carrier frequency with a high degree of precision.

The carrier is applied to the I and Q multipliers in quadrature

fashion (90° phase offset) and summed to yield a data stream

that is the modulated carrier. Note that the incoming data has

been converted from an input sample rate of fIN to an output

sample rate of SYSCLK (see Figure 23).

DATA

TxENABLE

DATA

ASSEMBLER

HALF-BAND

FILTER #1

HALF-BAND

FILTER #2

HALF-BAND

FILTER #3

DDS

INV

SINC

INV SINC

BYPASS

RSET

AOUT

M = 4...20

REFCLK

N = 2...63

(SYSCLK)

(F4)

(F3)

(F2)

(F1)

3, 6, 12

MUX

COS

SIN

CIC

FILTER

QUADRATURE

MODULATOR

MUX

DAC

HBF #3

BYPASS

HBF #3

BYPASS

MUX

÷2

MUX

HBF #3 BYPASS

÷N

(F5)

MUX

REFCLK

MULTIPLIER

(M)

÷2

Figure 23. AD9856 Block Diagram

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